In rapid wireless communication technology development environment, antennas, the interface among many wireless communications, are an indispensable component for wireless systems. Miniaturization and functionality stability (high tolerance to environmental variations) of the antenna are fast becoming the design trends in research and development of wireless communication systems. They are also the main objectives of this thesis. In the first part of this thesis, we designed two highly stable antennas, which can be used in notebook computers or tablet PCs. The antenna has self-balanced characteristics, where the environmental interference is minimized, in its performance/functionality and patterns. The first antenna design, which can be easily integrated into an RF front-end board, employed capacitive coupling, differential feed printed loop configurations. Comparing to the existing differentially fed antenna design, our designs are much more miniaturized: the antenna size was 13 mm ¡Ñ 27 mm, the ground size was 4.5 mm ¡Ñ 4.5 mm. Implemented on a low-cost FR4 board, the antenna reduced the leakage current formed on coaxial transmission line, due to the advantage of being differentially fed. The second antenna design, fed by coaxial cable (single-ended fed), and without a ground plane, excited only self-balanced modes. The radiation patterns of higher modes in this antenna design are complete and without side lobes. This antenna design also has wide bandwidth characteristics: at 2.4 GHz it had 380 MHz, and at 5.2 GHz it had 1270 MHz bandwidths of high tolerance (stability). The actual measurement validated our simulation results. In the second part, MIMO antennas were designed for 802.11n wireless standards with maximum transfer rates of up to 300 Mbps. First, we designed two small single antennas, which were applied later in MIMO antenna designs. The size of our MIMO antenna designs was only 19 mm ¡Ñ 30.3 mm. In MIMO antenna designs, we employed two methods to increase the isolation between the two MIMO antennas: one manipulated the ground plane size, in which the isolation reached 18.9 dB; the other utilized a decoupling metal, where the overall isolation reached 24.6 dB in all of the operating frequencies, with the best isolation being 31.4 dB. The frequency of the coupling/decoupling for the decoupling metal can be adjusted independently; thus not affecting the original resonant frequency and the return loss of the two MIMO antennas. Actual measurements conducted in the microwave chamber (Reverberation Chamber) have verified the channel capacity were effectively increased, the total radiation efficiencies were about 60%, and the effective diversity gain was about 7dB. The MIMO antenna designs can practically and easily applied in the USB dongles.

Abstract Whether an Open Area Test Site (OATS) is qualified is based on the Normalized Site Attenuation (NSA). The purpose is to eliminate the influence of Antenna Factor (AF). Usually the AF provided by the manufacturer adopts the Standard Site Method (SSM) and is quoted from measurements at a 10-m range. In practice, the AF varies with the measurement conditions. This uncertainly will translate into error in NSA measurements. Currently radiated electromagnetic interference measurement mostly adopts the broadband antennas, and LPDA is one of the antennas used extensively. However, the AF provided by the manufacturer does not consider shifts in the phase center of LPDA with frequency. In the meantime the radiation pattern of LPDA is different from that of a short dipole. The investigation of this thesis will focus on these two parts. In determining the phase center of LPDA antenna we adopt the average shift of phase center to improve the AF. The numerical simulation results show that such an arrangement can result in improvement. We also use the method of PCPM (Phase Center and Pattern Matching) to modify the AF under different conditions of measurement when a ground plane is present. Our study, by using the numerical simulation and measurement, shows that this indeed improves the variation of AF over that obtained by SSM. In addition, efforts are also made to have a detailed discussion in mutually coupling effects between the LPDA antenna and the ground plane, in order to distinguish the impact on AF due to the coupling of the LPDA antenna and its image. Our numerical simulation results indicate that it does not have a significant effect.

In many wireless devices, antennas occupy the majority of the overall size. As compact device sizes become a greater focus in industry, the demand for small antennas escalates. In this thesis, detailed investigations on the design of a planar meandered line antenna with truncated ground plane and 3D dipole antenna at 2.4 GHz (ISM band) are presented. The primary goal of this research is to develop small, low coast, and low profile antennas for wireless sensor applications. The planar meandered line antenna was designed based on a study of different miniaturization techniques and a study of the ground plane effect. The study of the ground plane effect proved that it has a pivotal role on balancing the antenna current. The study of the miniaturization process proved that it affects directly the gain, bandwidth, and efficiency. The antenna efficiency and gain were improved using the truncated ground plane. This antenna has a measured gain of -0.86 dBi and measured efficiency of 49.7%, making it one of the efficient and high gain small antennas. The 3D dipole antenna was designed using a novel method for efficiently exploiting the available volume. This method consists of fabricating the dipole on a cube configuration with opening up the internal volume for other uses. This antenna was tested, and it was found that this antenna has good radiation characteristics according to its occupied volume. Ka of this antenna is 0.55, its measured gain is 1.69 dBi with 64.2% measured efficiency. Therefore, this design is very promising in low-power sensing applications. A Wheeler Cap was designed for measuring the efficiency and the 3-antenna method was used for measuring the designed antennas gain.

Este trabalho apresenta um estudo do efeito do substrato em transistores SOI de camada de silício e óxido enterrado ultrafinos (Ultra Thin Body and Buried Oxide - UTBB). A análise do trabalho foi realizada baseando-se em modelos teóricos, simulações numéricas e medidas experimentais. Experimentalmente pode-se notar que a presença do plano de terra (Ground Plane, GP) abaixo do óxido enterrado elimina e/ou minimiza alguns efeitos indesejados do substrato, tais como a variação do potencial na terceira interface (óxido enterrado/substrato). A densidade de armadilhas de interfaces (Nit) foi um parâmetro importante no ajuste da simulação para se obter curvas de corrente de dreno (IDS) em função da tensão de porta (VGF) e em função da tensão de substrato (VGB) similares às experimentais. As densidades de armadilhas de interface da primeira e da segunda interface foram ajustadas para o valor de 2x1011eV-1cm-2 depois de analisadas as curvas experimentais. Assim, a partir dessas simulações pode-se notar que o modelo usado no simulador era compatível com os resultados experimentais, com erro menor que 10%. Observou-se que o modelo analítico de efeito do substrato proposto por Martino et al. para transistores SOI totalmente depletados com camadas de silício mais espessas (acima de 40 nm) pode ser utilizado para dispositivos UTBB SOI de canal longo (10 m) até a segunda interface (camada de silício/óxido enterrado) entrar em inversão, quando o modelo perde a validade. Utilizando o modelo analítico também foi possível determinar os valores de tensão de substrato máximo (VGBmax) e mínimo (VGBmin), que determinam a tensão que, aplicada no substrato, mudam o estado da terceira interface de inversão para depleção (VGBmin) e de depleção para acumulação (VGBmax). Os valores de VGBmax variaram de 0,57 V à 0,75 V e os de VGBmin de -0,08 V à -3,39 V. O modelo analítico utilizado tem uma concordância ainda maior (menor que 10%) para transistores de canal curto (L=70 nm) em relação ao de canal longo (L=10m), provavelmente devido ao acoplamento eletroestático de fonte/dreno e 6 canal que posterga a formação da camada de inversão da terceira interface, ampliando a faixa de validade do mesmo. Por meio das simulações numéricas também foi possível analisar a concentração de elétrons ao longo do canal do transistor. Observou-se que a condição de polarização da terceira interface (óxido enterrado/substrato) tem grande influência no comportamento da segunda interface (camada de Silício/óxido enterrado) e da primeira (óxido de porta/camada de Silício) nos transistores UTBB SOI. Quando a terceira interface (óxido enterrado/substrato) está em acumulação, a primeira interface possui uma concentração de elétrons menor que a segunda interface, caracterizando assim, uma condução maior pela segunda interface. O simulador também foi utilizado para analisar o potencial interno do transistor ao longo da profundidade. Foram feitas simulações com e sem GP e variando-se a temperatura de operação dos transistores. Foi observado que quanto maior a temperatura de operação, os efeitos do substrato são minimizados devido à diminuição do nível de Fermi. Com a presença do GP a queda de potencial no substrato é praticamente zero enquanto nos dispositivos sem GP variam entre 0,2V e 0,6V. Como nos dispositivos com GP a queda do potencial no substrato é praticamente zero, a queda nos óxidos aumentou em relação aos dispositivos sem GP, podendo causar problemas de confiabilidade. / This work presents a study of the substrate effect on Ultra Thin Body and Buried Oxide (UTBB) SOI transistors. The work analysis was performed based on theoretical models, numerical simulations and experimental measurements. Experimentally, it is possible to notice that the presence of the ground plane implantation (GP) below the buried oxide eliminates and/or minimizes some undesirable effects of the substrate, as the variation of potential drop on third interface (buried oxide/substrate). The interface trap density (Nit) was an important parameter on simulation adjustment to obtain drain current curves as function of front gate bias and back gate bias close to the experimental. The interface trap density of the front and back interface were adjusted to the value of 2x10¹¹ e V-1 cm-2 after the experimental curves were analyzed. So from these simulations, it can be verified that the model used in the simulator was compatible with the experimental results, with error < 10%. It is noted that the analytic model proposed by Martino et al. to analyze the substrate effect for fully depleted SOI transistor with thicker silicon thickness (above 40 nm) is useful for UTBB SOI devices with long channel (L=10 m) until the back interface reach the inversion, when the model is no longer valid. Using the analytic model, it was also possible to determine the values of VGBmax and VGBmin, which represents the back voltage required to change de third interface from inversion to depletion mode (VGBmin), and the depletion to accumulation mode (VGBmax). The value of VGBmax ranged from 0,57 V to 0,75 V and for VGBmin ranged from -0,08 V to -3,39 V. The analytic model has more agreement for short channel (L = 70nm) transistor than the longer one (L = 10m), probably due to the electrostatic coupling between de drain/source and the channel that delays the formation of inversion channel on third interface extending the validity range of the model. By the numerical simulation, it was possible to analyze the electron concentration along the transistor. It was observed that the mode of the third 8 interface influences directly the condition of the back and front interfaces on UTBB SOI transistor. When the third interface is in accumulation mode, the front interface has an electron concentration lower than the back interface, so the current flows mainly on the back interface. This makes the value of the front threshold voltage is less than the analytic model, once the model is valid only if while the back interface is on depletion mode. The numerical simulation was also used to analyze the potential drop on SOI transistor. Simulation was performed with and without GP and varying the temperature. It was observed that for higher temperature, the substrate effect was minimized dur to the decrease of the Fermi level towards the mid-band. With GP, the substrate potential drop is almost zero, while on devices without GP it changes from 0,2 V to 0,6 V For devices with GP the potential, as the drop on substrate is almost zero, the potential drop on front and buried oxide increases, which can causes reliability problems.

No description available.

This thesis presents an experimental investigation of drag reduction devices on a bluff body in ground effect. It has previously been shown that the addition of end-plate tabs to a rectangular based bluff body with an aspect ratio of 4 is effective in eliminating vortex shedding and reducing drag for low Reynolds number flows. In the present study a square based bluff body, both with and without tabs, will be tested under the same conditions, except this time operating within proximity to a ground plane in order to mimic the properties of bounded aerodynamics that would be present for a body in ground effect.

In recent years, the demand for compact handheld communication devices has grown significantly. Devices having internal antennas have appeared to fill this need. Antenna size is a major factor that limits device miniaturization. In the past few years, new designs based on the microstrip antennas (MSA) and planar inverted-F antennas have been used for handheld wireless devices because these antennas have low-profile geometry and can be embedded into the devices. New wireless applications requiring operation in more than one frequency band are emerging. Dual-band and tri-band phones have gained popularity because of the multiple frequency bands used for wireless applications. One prominent application is to include bluetooth, operating band at 2.4 GHz, for short-range wireless use. This thesis examines two antennas that are potential candidates for small and low-profile structures: microstrip antennas and planar inverted-F antennas. Two techniques for widening the antenna impedance bandwidth are examined by adding parasitic elements. Reducing antenna size generally degrades antenna performance. It is therefore important to also examine the fundamental limits and parameter tradeoffs involved in size reduction. In the handheld environment, antennas are mounted on a small ground plane. Ground plane size effects on antennas are investigated and the results from a thorough numerical study on the performance of a PIFA with various ground planes sizes and shapes is reported. Finally, a new wideband compact PIFA antenna (WC-PIFA) is proposed. Preliminary work is presented along with numerical and experimental results for various environments such as free space, plastic casing, and the proximity of a hand. This new antenna covers frequencies from 1700 MHz to 2500 MHz, which basically include the following operating bands: DCS-1800m PCS-1900, IMT-2000, ISM, and Bluetooth. / Master of Science

Esse trabalho tem como objetivo estudar o comportamento de transistores de camada de silício e óxido enterrado ultrafinos (UTBB SOI nMOSFET) e transistores de nanofios horizontais com porta ômega ? (?G NW SOI MOSFET) com ênfase na variação da tensão aplicada no substrato (VGB). As análises foram feitas através de medidas experimentais e simulações numéricas. Nos dispositivos UTBB SOI nMOSFET foram estudados dispositivos com e sem implantação de plano de terra (GP), de três diferentes tecnologias, e com diferentes comprimentos de canal. A partir do modelo analítico de tensão de limiar desenvolvido por Martino et al. foram definidos os valores de VGB. A tecnologia referência possui 6 nm de camada de silício (tSi) e no óxido de porta uma camada de 5 nm de SiO2. A segunda tecnologia tem um tSi maior (14 nm) em relação a referência e a terceira tecnologia tem no óxido de porta um material de alta constante dielétrica, HfSiO. Na tecnologia de referência, os dispositivos com GP mostraram melhores resultados para transcondutância na região de saturação (gmSAT) devido ao forte acoplamento eletrostático entre a região da porta e do substrato. Porém os dispositivos com GP apresentam uma maior influência do campo elétrico longitudinal do dreno no canal, assim os parâmetros condutância de saída (gD) e tensão Early (VEA) são degradados, consequentemente o ganho de tensão intrínseco (AV) também. Na tecnologia com tSi de 14 nm, a influência do acoplamento eletrostático entre porta e substrato é menor em relação a referência, devido à maior espessura de tSi. Como a penetração do campo elétrico do dreno é maior em dispositivos com GP, todos os parâmetros analógicos estudados são degradados em dispositivos com GP. A última tecnologia estudada, não apresenta grande variação nos resultados quando comparadodispositivos com e sem GP. O AV, por exemplo, tem uma variação entre 1% e 3% comparando os dispositivos com e sem GP. Foram feitas análises em dispositivos das três tecnologias com comprimento de canal de 70 nm, e todos os parâmetros degradaram com a diminuição do comprimento de canal, como esperado. O fato de ter um comprimento de canal menor faz com que a influência do campo elétrico longitudinal do dreno seja mais relevante, degradando assim todos os parâmetros analógicos nos dispositivos com GP. Nos dispositivos ?G NW SOI MOSFET foram feitas análises em dispositivos pMOS e nMOS com diferentes larguras de canal (WNW = 220 nm, 40 nm e 10 nm) para diferentes VGB. Através de simulações viu-se que dispositivos com largura de canal de 40 nm possuem uma condução de corrente pela segunda interface para polarizações muito altas (VGB = +20 V para nMOS e VGB -20 V para pMOS). Todavia essa condução de corrente na segunda interface ocorre ao mesmo tempo que na primeira interface, impossibilitando fazer a separação dos efeitos de cada interface.A medida que a polarização no substrato faz com que haja uma condução na segunda interface, todos os parâmetros degradam devido a essa condução parasitária. Dispositivos estreitos sofrem menor influência de VGB e, portanto, tem os parâmetros menos degradados, diferente dos dispositivos largos que tem uma grande influência de VGB no comportamento elétrico do transistor. Quando a polarização no substrato é feita a fim de que não haja condução na segunda interface, a variação da inclinação de sublimiar entre dispositivos com WNW = 220 nm e 10 nm é menor que 2 mV/déc. Porém a corrente de dreno de estado ligado do transistor (ION) apresenta melhores resultados em dispositivos largos chegando a 6 vezes maior para nMOS e 4 vezes maior para pMOS que em dispositivos estreitos. Os parâmetros analógicos sofrem pouca influência da variação de VGB. Os dispositivos estreitos (WNW = 10 nm) praticamente têm resultados constantes para gmSAT, VEA e AV. Já os dispositivos largos (WNW = 220 nm) possuem uma pequena degradação de gmSAT para os nMOS, o que degrada levemente o AV em cerca de 10 dB. A eficiência do transistor (gm/ID) apresentou grande variação com a variação de VGB, piorando-a a medida que a segunda interface ia do estado de não condução para o estado de condução. Porém analisando os dados para a tensão que não há condução na segunda interface observou-se que, em inversão forte, a eficiência do transistor apresentou uma variação de 1,1 V-1 entre dispositivos largos (WNW = 220 nm) e estreitos (WNW = 10 nm). Com o aumento do comprimento do canal, esse valor de variação tende a diminuir e dispositivos largos passam a ser uma alternativa válida para aplicação nessa região de operação. / This work aims to study the behavior of the ultrathin body and buried oxide SOI nMOSFET (UTBB SOI nMOSFET) and the horizontal ?-gate nanowire SOI MOSFET (?G NW SOI MOSFET) with the variation of the back gate bias (VGB). The analysis were made through experimental measures and numerical simulation. In the UTBB SOI nMOSFET devices, devices with and without ground plane (GP) implantation of three different technologies were studied. Based on analytical model developed by Martino et al. the values VGB were defined. The reference technology has silicon film thickness (tSi) of 6 nm and 5 nm of SiO2 in the front oxide. The second technology has a thicker tSi of 14 nm comparing to the reference and the third technology has a high-? material in the front oxide, HfSiO. In the reference technology, the devices with GP shows better result for transconductance on saturation region (gmSAT) due to the strong coupling between front gate and substrate. However, devices with GP have major influence of the drain electrical field penetration, then the output conductance (gD) and Early voltage (VEA) are degraded, consequently the intrinsic voltage gain (AV) as well. In the technology with tSi of 14 nm, the influence of the coupling between front gate and substrate is lower because of the thicker tSi. Once the drain electrical field penetration is higher in devices with GP, all analog parameters are degraded in devices with GP. The third technology, presents results very close between devices with and without GP. The AV has a variation from 1% to 3% comparing devices with and withoutGP. Devices with channel length of 70 nm were analyzed and all parameters degraded with the decrease of the channel length, as expected. Due to the shorter channel length, the influence of the drain electrical field penetration is more relevant, degrading all the analog parameters in devices with GP. In the ?G NW SOI MOSFET devices, the analysis were done in nMOS and pMOS devices with different channel width (WNW = 220 nm, 40 nm and 10 nm) for different VGB. By the simulations, devices with channel width of 40 nm have a conduction though the back interface for very high biases (+20 V for nMOS and -20 V for pMOS). However, this conduction occurs at the same time as in the front interface, so it is not possible to separate de effects of each interface. As the substrate bias voltage induces a back gate current, all the parameters are degraded due to this parasitic current. Narrow devices are less affected by VGB and thus its parameters are less degraded, different from wider devices, in which VGB has a greater influence on their behavior. When the back gate is biased in order to avoid the conduction in back interface, the subthreshold swing variation between devices with WNW = 220 nm and 10 nm is lower than 2 mV/déc. However, the on state current (ION) has better results in wide devices reaching 6 times bigger for nMOS and 4 times bigger for pMOS The analog parameterssuffer little influence of the back gate bias variation. The narrow devices (WNW = 10 nm) have practically constant results gmSAT, VEA and AV. On the other hand, wide devices (WNW = 220 nm) have a small degradation in the gmSAT for nMOS, which slightly degrades de AV. The transistor efficiency showed great variation with the back gate bias variation, worsening as the back interface went from non-conduction state to conduction state. However, when the back gate is biased avoiding the conduction in back interface, the transistor efficiency for strong inversion region has a small variation of 1,1 V-1 between wide (WNW = 220 nm) and narrow (WNW = 10 nm) devices. As the channel length increases, this value of variation tends to decrease and wide devices become a valid alternative for applications in this region of operation.

A mobile phone antenna with a radiating coupling feed is presented. By using the radiating coupling feed, the conventional coupled-fed loop antenna and coupled-fed shorted monopole antenna can be efficiently incorporated into the antenna structure and respectively excite a wide band resonant mode to cover GSM850/900 and GSM1800/1900/UMTS/LTE2300/2500 for the seven-band operation. Besides, the antenna can be in compact integration with the extended ground plane such that more electronic components in the mobile phone can be accommodated in the practical applications. In order to study the near-field radiation characteristics of the antenna, SAR and HAC are also simulated and analyzed.

Neste trabalho é apresentada uma análise da antena planar F-invertido (PIFA) com o objetivo de identificar os parâmetros geométricos que influenciam nas características de desempenho: frequência de ressonância, perda de retorno e largura de banda. Para realizar este estudo é desenvolvido um algoritmo em linguagem C baseado no método das Diferenças Finitas no Domínio do Tempo (FDTD). Duas PIFAs de geometria distintas foram investigadas. O primeiro modelo trata da geometria tradicional de elemento irradiador e plano de terra, ambos retangulares. Já o segundo modelo apresenta a fenda em formato de L no elemento irradiador, para operação em frequência dupla, e o plano de terra em formato de T, visando a aumentar a largura de banda. Os resultados da simulação do algoritmo identificam os parâmetros que influenciam no aumento nas duas larguras de banda, e são aplicados na prototipação de uma PIFA GSM-900 e GSM-1800. As medidas de laboratório do protótipo evidenciam os resultados previstos pelo algoritmo. / A Planar Inverted-F Antenna (PIFA) analysis is presented in this work, aiming to identify the geometric parameters that influence the antenna performance, such as resonant frequency, return loss and bandwidth. To accomplish this goal, an algorithm in C language based on the Finite-Difference Time-Domain (FDTD) method is developed. Two PIFAs with distinct geometries are investigated. The first one corresponds to a typicall rectangular patch and ground plane, The second model presents an L-shaped slot for dual frequency band operation, combined with a T-shaped ground plane, in order to increase the bandwidth. The simulated results obtained by algorithm identify the parameters that respond for both bandwidths enhancement, and are applied in a PIFA GSM-900/GSM-1800 practical project. The prototype’s measurements confirm the simulated results.