Hamming-distance graphs arise naturally in the study of error-correcting codes and have been utilized by several authors to provide new proofs for (and in some cases improve) known bounds on the size of block codes. We study various standard graph properties of the Hamming-distance graphs with special emphasis placed on the chromatic number. A notion of robustness is defined for colorings of these graphs based on the tolerance of swapping colors along an edge without destroying the properness of the coloring, and a complete characterization of the maximally robust colorings is given for certain parameters. Additionally, explorations are made into subgraph structures whose identification may be useful in determining the chromatic number.

Steganography is a technique which hides secret information. In this work, we will hide a secret information in the packets which are produced during a Skype call. Skype is one of the best known and the most widely used VoIP applications. We will propose, describe and implement a steganography method by which we will send the secret message during the Skype call. For embedding the message into packets and extracting them, we will use steganographic method called matrix encoding. To avoid packet loss, we will increase the robustness of this method by error-correcting and self-synchronising codes. As error-correcting codes, we will use the binary Hamming (7, 4) -codes and for the self-synchronising, we will use T-codes. 1

Submitted by JOSIANE SANTOS DE OLIVEIRA (josianeso) on 2017-05-25T12:10:45Z No. of bitstreams: 1 Elcio Kondo_.pdf: 2605139 bytes, checksum: bc6eb6e69a381723f69fbce90af22fab (MD5) / Made available in DSpace on 2017-05-25T12:10:45Z (GMT). No. of bitstreams: 1 Elcio Kondo_.pdf: 2605139 bytes, checksum: bc6eb6e69a381723f69fbce90af22fab (MD5) Previous issue date: 2017-01-11 / Nenhuma / Atualmente vários equipamentos eletrônicos são equipados com memórias NAND Flash para armazenar dados. Essas memórias são controladas através de um circuito integrado com um controlador de memória, que internamente possui um sistema para garantir a integridade das informações armazenadas, os quais são conhecidos por Error Correction Codes (ECC). Os ECCs são códigos capazes de detectar e corrigir erros através de bits redundantes adicionados à informação. Normalmente, os códigos ECC são implementados em hardware dentro do controlador de memória NAND Flash. Neste trabalho comparou-se alguns códigos de ECC utilizados pela indústria, para as comparações utilizou-se os códigos ECC: Hamming, BCH (Bose-Chaudhuri-Hocquenghem) e Reed- Solomon. Sistematicamente realizou-se comparações entre os ECCs selecionados e escolheu-se os dois mais apropriados (BCH e Hamming), os quais foram implementados em linguagem VHDL, o que possibilitou identificar o código com melhor vantagem econômica no uso em memórias NAND Flash. / Nowadays several electronic equipment are using NAND Flash memories to store data. These memories are controlled by an integrated circuit with an memory controller embedded that internally has a system to ensure the integrity of the stored information, that are known as Error Correction Codes (ECC). The ECCs are codes that can detect and correct errors by redundant bits added to information. Usually the ECC codes are implemented on NAND Flash memory controller as a hardware block. On this text ECC codes used by industry, the Hamming code, BCH (Bose-Chaudhuri-Hocquenghem) and Reed-solomon codes were compared.Systemically compare between selected ECCs were done and selected two codes (BCH and Hamming), which were described in VHDL language and allowed to identify the best code with better economical advantage for NAND Flash memories.

Let V denote a vector space of finite positive dimension. An ordered triple of linear operators on V is said to be a Leonard triple whenever for each choice of element of the triple there exists a basis of V with respect to which the matrix representing the chosen element is diagonal and the matrices representing the other two elements are irreducible tridiagonal. A Leonard triple is said to be modular whenever for each choice of element there exists an antiautomorphism of End(V) which fixes the chosen element and swaps the other two elements. We study combinatorial structures associated with Leonard triples and modular Leonard triples. In the first part we construct a simplicial complex of Leonard triples. The simplicial complex of a Leonard triple is the smallest set of linear operators which contains the given Leonard triple with the property that if two elements of the set are part of a Leonard triple, then the third element of the triple is also in the set. In the second part we construct a Hamming association scheme from modular Leonard triples using a method used previously in the context of Grassmanian codes.

Finding near-duplicate documents is an interesting problem but the existing methods are not suitable for large scale datasets and memory constrained systems. In this work, we developed approaches that tackle the problem of finding near-duplicates while improving query performance and using less memory. We then carried out an evaluation of our method on a dataset of 70M web documents, and showed that our method works really well. The results indicated that our method could achieve a reduction in space by a factor of 5 while improving the query time by a factor of 4 with a recall of 0.95 for finding all near-duplicates when the dataset is in memory. With the same recall and same reduction in space, we could achieve an improvement in query-time by a factor of 4.5 while finding first the near-duplicate for an in memory dataset. When the dataset was stored on a disk, we could achieve an improvement in performance by 7 times for finding all near-duplicates and by 14 times when finding the first near-duplicate.

In this thesis, bit-by-bit power allocation in order to minimize mean-squared error (MSE) distortion of a basic communication system is studied. This communication system consists of a quantizer. There may or may not be a channel encoder and a Binary Phase Shift Keying (BPSK) modulator. In the quantizer, natural binary mapping is made. First, the case where there is no channel coding is considered. In the uncoded case, hard decision decoding is done at the receiver. It is seen that errors that occur in the more significant information bits contribute more to the distortion than less significant bits. For the uncoded case, the optimum power profile for each bit is determined analytically and through computer-based optimization methods like differential evolution. For low signal-to-noise ratio (SNR), the less significant bits are allocated negligible power compared to the more significant bits. For high SNRs, it is seen that the optimum bit-by-bit power allocation gives constant MSE gain in dB over the uniform power allocation. Second, the coded case is considered. Linear block codes like (3,2), (4,3) and (5,4) single parity check codes and (7,4) Hamming codes are used and soft-decision decoding is done at the receiver. Approximate expressions for the MSE are considered in order to find a near-optimum power profile for the coded case. The optimization is done through a computer-based optimization method (differential evolution). For a simple code like (7,4) Hamming code simulations show that up to 3 dB MSE gain can be obtained by changing the power allocation on the information and parity bits. A systematic method to find the power profile for linear block codes is also introduced given the knowledge of input-output weight enumerating function of the code. The information bits have the same power, and parity bits have the same power, and the two power levels can be different.

A product turbo code (PTC) decoder application specific integrated circuit (ASIC) is designed in 0.18μm 1P6M CMOS with embedded SRAM. From simulation, an operating frequency of 73.1 MHz at typical conditions is obtained, yielding a throughput of 3.8 Mbps with 4 decoding iterations, while consuming 103.4 mW. The total area is 5.13 mm2. Assuming the ASIC would be used as a hard macro, the area could be reduced to 1.7 mm2. The ASIC was tested at 20 MHz under typical conditions, which resulted in a throughput of 1.0 Mbps at 1.8V supply while consuming 36.6 mW. By making a slight modification, this design can be easily scaled to support IEEE 802.16d WiMAX. Allow for this, and moving to a 45nm process an estimated throughput of 9.44 Mbps with 4 iterations can be obtained. Total macro area would be approximately 0.11 mm2.

A product turbo code (PTC) decoder application specific integrated circuit (ASIC) is designed in 0.18μm 1P6M CMOS with embedded SRAM. From simulation, an operating frequency of 73.1 MHz at typical conditions is obtained, yielding a throughput of 3.8 Mbps with 4 decoding iterations, while consuming 103.4 mW. The total area is 5.13 mm2. Assuming the ASIC would be used as a hard macro, the area could be reduced to 1.7 mm2. The ASIC was tested at 20 MHz under typical conditions, which resulted in a throughput of 1.0 Mbps at 1.8V supply while consuming 36.6 mW. By making a slight modification, this design can be easily scaled to support IEEE 802.16d WiMAX. Allow for this, and moving to a 45nm process an estimated throughput of 9.44 Mbps with 4 iterations can be obtained. Total macro area would be approximately 0.11 mm2.

Steganography is a technique which hides secret information. In this work, we will hide a secret information in the packets which are produced during a Skype call. Skype is one of the best known and the most widely used VoIP applications. We will propose, describe and implement a steganography method by which we will send the secret message during the Skype call. For embedding the message into packets and extracting them, we will use steganographic method called matrix encoding. To avoid packet loss, we will increase the robustness of this method by error-correcting and self-synchronising codes. As error-correcting codes, we will use the binary Hamming (7, 4) -codes and for the self-synchronising, we will use T-codes. 1

Masters of Science / Codes Related to and Derived from Hamming Graphs T.R Muthivhi M.Sc thesis, Department of Mathematics, University of Western Cape For integers n; k 1; and k n; the graph 􀀀k n has vertices the 2n vectors of Fn2 and adjacency de ned by two vectors being adjacent if they di er in k coordinate positions. In particular, 􀀀1 n is the classical n-cube, usually denoted by H1(n; 2): This study examines the codes (both binary and p-ary for p an odd prime) of the row span of adjacency and incidence matrices of these graphs. We rst examine codes of the adjacency matrices of the n-cube. These have been considered in [14]. We then consider codes generated by both incidence and adjacency matrices of the Hamming graphs H1(n; 3) [12]. We will also consider codes of the line graphs of the n-cube as in [13]. Further, the automorphism groups of the codes, designs and graphs will be examined, highlighting where there is an interplay. Where possible, suitable permutation decoding sets will be given.