Medical devices processing images or audio or executing complex AI algorithms are able to run more efficiently and meet real time requirements if the parallelism in those algorithms is exploited. In this research a methodology is proposed to exploit the flexibility and short design cycle of FPGAs (Field Programmable Gate Arrays) in order to achieve this target. Hardware/software co-design and dynamic partitioning allow the optimization of the multiprocessor platform design parameters and software code targeting each core to meet real time constraints. This is practically demonstrated by building a real life driver vigilance monitoring system based on visual cues extraction and evaluation. The application drives the whole design process to prove its effectiveness. An algorithm was built to achieve the goal of detecting the eye state of the driver (open or closed) and it is applied on captured consecutive frames to evaluate the vigilance state of the driver. Vigilance state is measured depending on duration of eye closure. This video processing application is then targeted to run on a multi-core FPGA based processing platform using the proposed methodology. Results obtained were very good using the Grimace Face Database and when operating the system on one’s face. On operating the device, a false positive of eye closure must take place two consecutive times in order to get an alarm, which decreases the probability of failure. The timing analysis applied proved the importance of using the concept of parallelism to achieve performance constraints. FPGA technology proved to be a very powerful prototyping tool for complex multiprocessor systems design. The flexible FPGA technology coupled with hardware/software co-design provided means to explore the design space and reach decisions that satisfy the design constraints with minimum time investment and cost.

Medical devices processing images or audio or executing complex AI algorithms are able to run more efficiently and meet real time requirements if the parallelism in those algorithms is exploited. In this research a methodology is proposed to exploit the flexibility and short design cycle of FPGAs (Field Programmable Gate Arrays) in order to achieve this target. Hardware/software co-design and dynamic partitioning allow the optimization of the multiprocessor platform design parameters and software code targeting each core to meet real time constraints. This is practically demonstrated by building a real life driver vigilance monitoring system based on visual cues extraction and evaluation. The application drives the whole design process to prove its effectiveness. An algorithm was built to achieve the goal of detecting the eye state of the driver (open or closed) and it is applied on captured consecutive frames to evaluate the vigilance state of the driver. Vigilance state is measured depending on duration of eye closure. This video processing application is then targeted to run on a multi-core FPGA based processing platform using the proposed methodology. Results obtained were very good using the Grimace Face Database and when operating the system on one’s face. On operating the device, a false positive of eye closure must take place two consecutive times in order to get an alarm, which decreases the probability of failure. The timing analysis applied proved the importance of using the concept of parallelism to achieve performance constraints. FPGA technology proved to be a very powerful prototyping tool for complex multiprocessor systems design. The flexible FPGA technology coupled with hardware/software co-design provided means to explore the design space and reach decisions that satisfy the design constraints with minimum time investment and cost.

For the next generation of multimedia applications such as digital video broadcasting, multimedia message service and video conference, enormous amounts of video context will be transmitted and exchanged through the wireless channel. Due to the limited communication bandwidth, how to achieve more efficient, reliable, and robust video compression is a very important issue. H.264/AVC (Advanced Video Coding) is one of the latest video coding standards, which is anticipated to be adopted in many future application systems due to its excellent compression efficiency. In this thesis, the implementation issue of the H.264 decoding algorithm on the SOC (System-On-Chip) development platform is addressed. Several key modules of H.264 decoders including color space converter, inter-interpolation, transformation rescale modules are all realized by dedicated hardware architectures. A novel low-cost fast scalable deblocking filter based on single-port memory architecture is also proposed which can support fast real-time deblocking filtering process. The entire H.264 decoder system is prototyped on the Altera SOPC platform, and the decoding result is displayed directly on the monitor. All the hardware modules are hooked on the system Avalon bus, and interact with Altera NIOS-¢º processor. Through the hardware/software co-design approach, the decoding speed can be increase by a factor of 1.9.

In diesem Beitrag wird eine Methode zur Beschreibung von Kostenfaktoren und deren Verknüpfung über Hierarchiegrenzen hinweg dargestellt. Sie eignet sich sowohl für rein digitale Systeme mit Softwareanteilen als auch für gemischt analog/digitale Systeme. Damit ist sie im Hardware-Software Codesign und im Analog-Digital Codesign zum Vergleich verschiedener Systemkompositionen anwendbar. Die Implementierung mit C++ ermöglicht neben einer Nutzung mit digitalem SystemC auch den Einsatz mit der analogen SystemC-Erweiterung SystemC-AMS und vereinfacht die Nutzung gegenüber einer vorhandenen VHDL-Implementierung. Als Anwendungsbeispiel fungieren Komponenten eines Systems zur Inertialnavigation.

In this thesis, an 8-bit microcontroller, 8051 core, is implemented using SystemC programming language. SystemC is a new generation co-design language which is capable of both programming software and describing hardware parts of a complete system. The benefit of this design environment appears while developing a System-on-Chip (SoC), that is a system consisting both custom hardware parts and embedded software parts. SystemC is not a completely new language, but based on C++ with some additional class libraries and extensions to handle hardware related concepts such as signals, multi-valued logic, clock and delay elements. 8051 is an 8 bit microcontroller which is widely used in industry for many years. The 8051 core is still being used as the main controller in today&rsquo / s highly complex chips, such as communication and bus controllers. During the development cycles of a System-on-Chip, instead of using separate design environments for hardware and software parts, the usage of a unified co-design environment provides a better design and simulation methodology which also decreases the number of iterations at hardware software integration. In this work, an 8-bit 8051 microcontroller core and external memory modules are developed using SystemC that can be re-used in future designs to achieve more complex System-on-Chip&rsquo / s. During the development of the 8051 core, simulation results are analyzed at each step to verify the design from the very beginning of the work, which makes the design processes more structured and controlled and faster as a result.

Made available in DSpace on 2014-06-12T15:58:54Z (GMT). No. of bitstreams: 1 license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2003 / Hardware/software co-design é uma metodologia utilizada para o desenvolvimento de sistemas digitais compostos por componentes de software e por componentes de hardware, que possibilita obter um drástico ganho de produtividade no desenvolvimento de tais sistemas. Este ganho de produtividade pode ser utilizado na exploração de diversas alternativas de solução, a fim de se conseguir melhorar a qualidade e reduzir o custo do projeto final. Com o recente crescimento da utilização de sistemas embarcados distribuídos, os projetistas têm cada vez mais utilizado ambientes de hardware/software co-design que suportem esta categoria de projetos. O co-design de sistemas embarcados distribuídos é uma tarefa ainda mais desafiadora, pois cada fase da metodologia tem que considerar as restrições físicas impostas pelas características distribuídas destes sistemas. Um dos desafios do co-design de sistemas embarcados distribuídos está na geração de comunicação entre processos alocados em diferentes sistemas embarcados. Trata-se de uma tarefa tediosa, propícia a erros e que consome bastante tempo quando não é realizada automaticamente, pois, a cada nova situação a ser analisada, a ausência de uma ferramenta de auxílio ao projeto força o projetista do sistema a refazer todos os parâmetros que são dependentes da aplicação e customizar os subsistemas de comunicação de maneira a refletir a nova arquitetura a ser analisada. O objetivo principal desse trabalho foi o desenvolvimento de um ambiente que gere automaticamente uma biblioteca de componentes de comunicação para sistemas embarcados que estão distribuídos. O sistema deve suportar projetos de diferentes escalas e com topologia qualquer. Para tanto, foi definido um modelo de comunicação, foi proposta uma arquitetura de rede para a qual o sistema deve gerar os componentes de comunicação e foi realizado o desenvolvimento de uma biblioteca de componentes de comunicação com especificações de implementação em hardware e em software, que suportam inclusive comunicação através da Internet. Como resultado do trabalho, foi implementado um sistema de geração automática de componentes de comunicação, GCCom, que oferece suporte ao desenvolvimento de projetos de sistemas embarcados distribuídos

In order to protect the security of the commercial information, personnel information, military information, governmental information on the Internet, the claimed identity should be authenticated. Now there are three main security authentication methods: first: using user PIN, such as password; second: using physical key, such as USBKey; third: using biological authentication technology, such as fingerprint, iris, voice and palm prints, etc. Because of the uniqueness, invariance, and ubiquity properties of biometric authentication, biometric authentication is becoming popular, especially fingerprint recognition. However, when the fingerprint recognition information is transported on the public channel, it may be attacked, such as the fingerprint information is stolen. So a cryptology mechanism is needed to protect the fingerprint recognition information. In the field of embedded security authentication system, the traditional hardware implementation mechanism, such as ASIC, can satisfy requires of functions and performances, but it is not configurable, flexible, and easy to expand; the traditional software implementation mechanism, such as general purpose processor, is flexible, but the cost and the power consumption are higher than hardware implementation. In order to take the advantages of biometrics, cryptology, hardware implementation, and software implementation, a hardware-software cooperating embedded authentication system based on shared-key authentication and fingerprint verification is proposed. First, this system authenticates the identities of client and server by shared-key authentication, creates the current encrypt key and hash key, and then authenticates the identity of them via fingerprint recognition. During fingerprint recognition, the information of fingerprint is not needed to transmit over the public channel, so the security of fingerprint is increased. Theoretic analysis and experiments show that, this system reach very high authentication rate and security. This system can resist replay attack, server template attack, device template attack, effectively.

An FPGA-based experiment platform for hardware-software codesign experiments was developed. The proposed platform would be used by an engineer who can be affiliated with academia, research or industry for codesign experiments or hardware emulation. The platform utilizes a combination of a microcontroller and a FPGA device to enable sufficient flexibility in exploring the design space to implement codesign experiments. The FPGA device operation is integrated with that of the microcontroller to provide an overall embedded solution for codesign experimentations. It is anticipated that the platform will be used in academia for educating the students the concepts of computer architecture and microprocessor design. Future work suggested includes development of performance metrics of hardware and software solutions, and in the partitioning stage of the codesign flow.

With the increasing adoption of Deep Neural Networks (DNNs) in modern applications, there has been a proliferation of computationally and power-hungry workloads, which has necessitated the use of embedded systems with more sophisticated, heterogeneous approaches to accommodate these requirements. One of the major solutions to tackle these challenges has been the development of domain-specific accelerators, which are highly optimized for the computationally intensive tasks associated with DNNs. These accelerators are designed to take advantage of the unique properties of DNNs, such as parallelism and data locality, to achieve high throughput and energy efficiency. Domain-specific accelerators have been shown to provide significant improvements in performance and energy efficiency compared to traditional general-purpose processors and are becoming increasingly popular in a range of applications such as computer vision and speech recognition. However, designing these architectures and managing their resources can be challenging, as it requires a deep understanding of the workload and the system's unique properties. Achieving a favorable balance between performance and power consumption is not always straightforward and requires careful design decisions to fully exploit the benefits of the underlying hardware. This dissertation aims to address these challenges by presenting solutions that enable low energy consumption without compromising performance for heterogeneous embedded systems. Specifically, this dissertation will focus on three topics: (i) the utilization of approximate computing concepts and approximate accelerators for energy-efficient DNN inference,(ii) the integration of formal properties in the systematic employment of approximate computing concepts, and (iii) resource management techniques on heterogeneous embedded systems.In summary, this dissertation provides a comprehensive study of solutions that can improve the energy efficiency of heterogeneous embedded systems, enabling them to perform computationally intensive tasks associated with modern applications that incorporate DNNs without compromising on performance. The results of this dissertation demonstrate the effectiveness of the proposed solutions and their potential for wide-ranging practical applications.

Multifunctional voltage source converters (VSCs) are desired for shipboard power systems. The opportunity to extend the functionality of a particular VSC on demand, combined with power system reconfiguration strategies may provide desired redundancy to back up power electronic converters that might be destroyed as a result of a battle damage or material casualty. The space for power electronics may be downsized if the VSCs are capable of performing multiple functions. In addition, the flexibility of the energy management can be enhanced in shipboard power systems if a single VSC can perform multiple functions. The functionality of a VSC in many cases is restricted to a single task or set of tasks by its control architecture. Despite the great number of different control strategies suggested for VSCs, nearly all use similar methods for generation of the reference signals. These methods generally depend upon the use of filters to extract reference signals for the components that are to be injected into or drawn from the system. These methods of control are not flexible. The main objective of the dissertation is the development of a flexible reference signal generator for VSCs that allows online maximization of its possible functions. Furthermore, the switching frequency of a VSC is generally above 10 kHz for many applications, and carries a significant amount of high frequency noise. This necessitates the use of EMI filters, which carry an extra cost and increase the overall bulk of the power electronics. This may not be acceptable for shipboard power systems, where the space and weight requirements are usually stringent. Thus, in addition to investigation of various reference signal generator (RSG) strategies for VSCs, alternative solutions to attenuate EMI levels in the shipboard power system environment are explored.