International Telemetering Conference Proceedings / October 29-November 02, 1990 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Modem microcomputers are proving to be viable hosts for telemetry functions, including data simulators. A specialized high-performance hardware architecture for generating and processing simulator data can be implemented on an add-in card for the microcomputer. Support software implemented on the host provides a simple, high-quality human interface with a high degree of user programmability. Based on this strategy, the Physical Science Laboratory at New Mexico State University (PSL) is developing a Programmable PCM Data Simulator for microcomputer hosts. Specifications and hardware/software architectures for PSL’s Programmable PCM Data Simulator are discussed, as well as its interactive user interface.

Cette étude a été consacrée à l'analyse et à la simulation du bruit des oscillateurs afin de l'appliquer à des VCO (Voltage Controlled Oscillator) pour des circuits intégrés à la Fréquence Intermédiaire dans le domaine des téléviseurs. Une méthode de simulation originale de la fluctuation de période en mode transitoire a été mise au point grâce au simulateur du bruit en transitoire présent dans le simulateur ELDO et à un extracteur de la valeur de la période (basé sur le langage ELDO-FAS). Le premier VCO, basé sur une architecture utilisant un circuit résonnant LC (inductance-capacité) a été conçu et réalisé. L'inductance est située à l'extérieur de la puce. La variation de fréquence est produite par une capacité variable. Le problème majeur de cette capacité (déphasage parasite du courant capacitif) a été compensé de façon originale. Le bruit de phase de ce VCO a été mesuré, simulé de plusieurs façons, avec une bonne corrélation. La simulation de la fluctuation de période a été validée. Un second VCO, à relaxation, complètement intégré (il ne requiert aucun composant externe), devant remplacer le premier, a été conçu. Son architecture est basée sur des éléments RC (résistance-capacité) en mode différentiel. Il peut fonctionner sous une faible tension d'alimentation (5V). Son bruit de phase a été optimisé à l'aide de la méthode de simula-tion<br />des variations de période mentionnée plus haut.

Advances in microelectronics allow the integration of more andmore functionality on a single chip. Emerging system-on-a-chiparchitectures include a large amount of heterogeneous componentsand are of increasing complexity. Applications using thesearchitectures require many low-level details in order to yield anefficient implementation. On the other hand constanttime-to-market pressure on electronic systems demands a shortdesign process that allows to model a system at a highabstraction level, not taking low-level implementation detailsinto account. Clearly there is a significant abstraction gapbetween an ideal model for specification and another one forimplementation. This abstraction gap has to be addressed bymethodologies for electronic system design. This thesis presents the ForSyDe (Formal System Design)methodology, which has been developed with the objective to movesystem design to a higher level of abstraction and to bridge theabstraction gap by transformational design refinement. ForSyDe isbased on carefully selected formal foundations. The initialspecification model uses a synchronous model of computation,which separates communication from computation and has anabstract notion of time. ForSyDe uses the concept of processconstructors to implement the synchronous model, to allow fordesign transformation and the mapping of a refined model onto thetarget architecture. The specification model is refined into adetailed implementation model by the stepwise application ofwell-defined design transformation rules. These rules are eithersemantic preserving or they inflict a design decision modifyingthe semantics. These design decisions are used to introduce thelow-level implementation details that are needed for an efficientimplementation. The implementation model is mapped onto thecomponents of the target architecture. At present ForSyDe modelscan be mapped onto VHDL or C/C++ in order to allow commercialtools to generate custom hardware or sequential software. Thethesis uses a digital equalizer to illustrate the concepts andpotential of ForSyDe. Electronic System Design, Hardware/Software Co-Design,Electrical Engineering

<p>Advances in microelectronics allow the integration of more andmore functionality on a single chip. Emerging system-on-a-chiparchitectures include a large amount of heterogeneous componentsand are of increasing complexity. Applications using thesearchitectures require many low-level details in order to yield anefficient implementation. On the other hand constanttime-to-market pressure on electronic systems demands a shortdesign process that allows to model a system at a highabstraction level, not taking low-level implementation detailsinto account. Clearly there is a significant abstraction gapbetween an ideal model for specification and another one forimplementation. This abstraction gap has to be addressed bymethodologies for electronic system design.</p><p>This thesis presents the ForSyDe (Formal System Design)methodology, which has been developed with the objective to movesystem design to a higher level of abstraction and to bridge theabstraction gap by transformational design refinement. ForSyDe isbased on carefully selected formal foundations. The initialspecification model uses a synchronous model of computation,which separates communication from computation and has anabstract notion of time. ForSyDe uses the concept of processconstructors to implement the synchronous model, to allow fordesign transformation and the mapping of a refined model onto thetarget architecture. The specification model is refined into adetailed implementation model by the stepwise application ofwell-defined design transformation rules. These rules are eithersemantic preserving or they inflict a design decision modifyingthe semantics. These design decisions are used to introduce thelow-level implementation details that are needed for an efficientimplementation. The implementation model is mapped onto thecomponents of the target architecture. At present ForSyDe modelscan be mapped onto VHDL or C/C++ in order to allow commercialtools to generate custom hardware or sequential software. Thethesis uses a digital equalizer to illustrate the concepts andpotential of ForSyDe.</p><p>Electronic System Design, Hardware/Software Co-Design,Electrical Engineering</p>

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Made available in DSpace on 2014-06-12T15:59:28Z (GMT). No. of bitstreams: 2 arquivo5129_1.pdf: 1241668 bytes, checksum: f51ca348f57f1072bfe811018105944c (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2002 / Este trabalho apresenta uma arquitetura Hardware/Software para aplicações em processamento de imagens. O sistema tem como intuito a implementação de um sistema de visão computacional direcionado ao controle de tráfego urbano, o qual visa detectar a presença de veículos em uma área de interesse, dentro do campo visual capturado por uma câmera de vídeo digital instalada em uma via pública. A metodologia de trabalho contempla o desenvolvimento inicial do algoritmo de processamento de imagens digitais através de ferramentas de alto nível de abstração (IDL - Interactive Data Language), explorando as alternativas de implementação com experimentos e técnicas de realce e análise das imagens. Na sequência do fluxo do projeto adotado, a etapa seguinte constitui-se na tradução das funções que compõem o algoritmo desenvolvido em linguagens de médio nível (C/C++), desenvolvendo um código executável que implementa o algoritmo e agregando controle ao usuário do sistema acerca dos ajustes funcionais e resultados obtidos no processamento. Dentro da metodologia de projeto hardware/ software, trechos do algoritmo que representam grande demanda do tempo de processamento, tais como filtragens por convolução foram migradas para uma implementação em hardware do processo, mapeando em um dispositivo de lógica programável a síntese lógica da descrição de hardware (VHDL - Very high speed integrated circuit Hardware Description Language), no intuito de satisfazer os requisitos temporais do sistema

<div> Due to a combination of algorithmic advances, wide-spread availability of rich data sets, and tremendous growth in compute availability, Deep Neural Networks (DNNs) have seen considerable success in a wide variety of fields, achieving state-of-the art accuracy in a number of perceptual domains, such as text, video and audio processing. Recently, there have been many efforts to extend this success in the perceptual, Euclidean-based domain to non-perceptual tasks, such as task planning or reasoning, as well as to non-Euclidean domains, such as graphs. While several DNN accelerators have been proposed in the past decade, they largely focus on traditional DNN workloads, such as Multi-layer Perceptions (MLPs), Convolutional Neural Networks (CNNs), and Recurrent Neural Networks (RNNs). These accelerators are ill-suited to the unique computational needs of the emerging neural networks. In this dissertation, we aim to fix this gap by proposing novel hardware architectures that are specifically tailored to emerging neural workloads.</div><div><br></div><div>First, we consider memory-augmented neural networks (MANNs), a new class of neural networks that exhibits capabilities such as one-shot learning and task planning that are well beyond those of traditional DNNs. MANNs augment a traditional DNN with an external differentiable memory that is used to store dynamic state. This dissertation proposes a novel accelerator that targets the main bottleneck of MANNs: the soft reads and writes to this external memory, each of which requires access to all the memory locations.</div><div><br></div><div>We then focus on Transformer networks, which have become very popular for Natural Language Processing (NLP). A key to the success of these networks is a technique called self-attention, which employs a softmax operation. Softmax is poorly supported in modern, matrix multiply-focused accelerators since it accounts for a very small fraction of traditional DNN workloads. We propose a hardware/software co-design approach to realize softmax efficiently by utilize a suite of approximate computing techniques.</div><div><br></div><div>Next, we address graph neural networks (GNNs). GNNs are achieving state-of-the-art results in a variety of fields such as physics modeling, chemical synthesis, and electronic design automation. These GNNs are a hybrid between graph processing workloads and DNN workloads; they utilize DNN-based feature extractors to form hidden representations for each node in a graph and then combine these representations through some form of a graph traversal. As a result, existing hardware specialized for either graph processing workloads or DNN workloads is insufficient. Instead, we design a novel architecture that balances the needs of these two heterogeneous compute patterns. We also propose a novel feature dimension-blocking dataflow to further increase performance by mitigating the memory bottleneck.</div><div><br></div><div>Finally, we address the growing difficulty in tightly coupling new DNNs and a hardware platform. Given the extremely large DNN-HW design space consisting of DNN selection, hardware operating condition, and DNN-to-HW mapping, it is infeasible to exhaustively search this space by running each sample on a physical hardware device. This has led to the need for highly accurate, machine learning-based performance models which can \emph{predict} the latency/power/energy even faster than direct execution. We first present a taxonomy to characterize the possible approaches to these performance estimators. Based on the insights from this taxonomy, we present a new performance estimator that combines coarse-grained and fine-grained to achieve superior accuracy with a limited number of training samples. Finally, we propose a flexible framework for creating these DNN-HW performance estimators.</div><div><br></div><div>In summary, this dissertation identifies the growing gap between current hardware and new emerging neural networks. We first propose three novel hardware architectures that address this gap for MANNs, Transformers, and GNNs. We then propose a novel hardware-aware DNN estimator and framework to ease addressing this gap for new networks in the future.</div>

Simulators are important tools for analyzing and evaluating different design options for wireless sensor networks (sensornets) and hence, have been intensively studied in the past decades. However, existing simulators only support evaluations of protocols and software aspects of sensornet design. They cannot accurately capture the significant impacts of various hardware designs on sensornet performance. As a result, the performance/energy benefits of customized hardware designs are difficult to be evaluated in sensornet research. To fill in this technical void, in this thesis, we describe the design and implementation of SUNSHINE, a scalable hardware-software cross-domain simulator for sensornet applications. SUNSHINE is the first sensornet simulator that effectively supports joint evaluation and design of sensor hardware and software performance in a networked context. SUNSHINE captures the performance of network protocols, software and hardware up to cycle-level accuracy through its seamless integration of three existing sensornet simulators: a network simulator TOSSIM, an instruction-set simulator SimulAVR and a hardware simulator GEZEL. SUNSHINE solves challenging design problems, including data exchanges and time synchronizations across different simulation domains and simulation accuracy levels. SUNSHINE also provides hardware specification scheme for simulating flexible and customized hardware designs. Several experiments are given to illustrate SUNSHINE's cross-domain simulation capability, demonstrating that SUNSHINE is an efficient tool for software-hardware codesign in sensornet research. / Master of Science