Le travail exposé dans cette thèse cible les nouveaux matériaux susceptibles d'être intégrés dans les mémoires et les applications à base de transistors MOS. Il est divisé en trois chapitres principaux. Le premier chapitre traite des contraintes de fabrication des dispositifs. Nous abordons aussi l'état de l'art ainsi que les objectifs industriels à courte échéance. Ce premier chapitre est important pour donner au lecteur les bases technologiques pour comprendre pourquoi des investissements gigantesques sur ces matériaux sont consentis dans l'industrie microélectronique et la recherche associée. Le second chapitre traite des méthodes de dépôt et croissance des isolants étudiés dans cette thèse. De même nous décrivons au mieux les moyens de caractérisation pour analyser les propriétés physiques et électriques de ces diélectriques. Quelques exemples de matériaux analysés aideront le lecteur à comprendre facilement notre méthode d'investigation scientifique. Le dernier chapitre est une revue de mon travail publié dans des journaux scientifiques de renommée internationale ou d'exposés dans des conférences majeures. Ce chapitre 3 est sous-divisé en 3 sections. La première et deuxième traite de la compréhension des propriétés des silicates d'aluminium-lanthane et oxydes de terre rare obtenus par différentes méthodes de dépôt et recuit. Les résultats ajoutés aux résultats de l'art antérieur donnent un aperçu significatif de notre recherche d'un matériau candidat potentiel comme isolant high k. La dernière section est dédiée aux oxydes de titane et de silicates de titane.

Dy-incorporated HfO₂ gate oxide with TaN gate electrode nMOS device has been developed for high performance CMOS applications in 22nm node technology. DyO /HfO bi-layer structure shows thin EOT with reduced leakage current and less charge trapping compared to HfO₂. Excellent electrical performance of the DyO-capped HfO₂ oxide n-MOSFET such as lower V[subscript TH], higher drive current, and improved channel electron mobility are reported. DyO/HfO samples also show better immunity for V[subscript TH] instability and less severe charge trapping characteristics. Its charge trapping characteristics, conduction mechanisms and dielectric reliability have been investigated in this work. As an application to memory device, HfON charge trapping layered NAND flash memory is developed and characterized. First, temperature-dependent Dy diffusion and the diffusion-driven Dy dipole formation process are discussed to clarify the origin of V[subscript TH] shift, and eventually modulate the effective work function in Dy-Hf-O/SiO₂ system. The Dy-induced dipoles are closely related to the Dy-silicate formation at the high-k/SiO₂ interfaces since the V[subscript FB] shift in Dy₂O₃ is caused by the dipole and coincides with the Dy-silicate formation. Dipole formation is a thermally activated process, and more dipoles are formed at a higher temperature with a given Dy content. The Dy-silicate related bonding structure at the interface is associated with the strength of the Dy dipole moment, and becomes dominant in controlling the V[subscript FB]/V[scubscript TH] shift during high temperature annealing in the Dy- Hf-O/SiO₂ gate oxide system. Dy-induced dipole reduces the degradation of the electron mobility. Second, to understand the reduced leakage current of the DyO/HfO sample, the effective barrier height of Dy₂O₃ was calculated from FN tunneling models, and the band diagram was estimated. The higher effective barrier height of Dy₂O₃, which is around 2.32 eV calculated from the F-N plot, accounts for the reduced leakage current in Dy incorporated HfO₂ nMOS devices. The lower barrier height of HfO₂ result in increased electron tunneling currents enhanced by the buildup of hole charges trapped in the oxide, which causes a severe increase of stress-induced leakage current (SILC), leading to oxide breakdown. However, the increased barrier height in Dy incorporated HfO₂ inhibits a further increase of the electron tunneling from the TaN gate, and trapped holes lessen the hole tunneling currents, resulting in a negligible SILC. The lower trap generation rate by the reduced hole trap density and the reduced hole tunneling of the Dy-doped HfO₂ dielectric demonstrates the high dielectric breakdown strength by weakening the charge trapping and defect generation during the stress. Based on these fundamental studies of the dielectric breakdown, modeling of time-dependent dielectric breakdown (TDDB) was done. The intrinsic TDDB of the Dy-doped HfO₂ gate oxide having 1 nm EOT is characterized by the progressive breakdown (PBD) model. At high temperature, the PBD becomes severe, since thermal energy causes carrier hopping between the localized weak spots. The voltage acceleration factor derived from the power law shows a realistic prediction in comparison with those from the 1/E model. The increase of the voltage acceleration factor at lower stress voltage is due to the lower trap generation rate in Dy- incorporated HfO₂. This voltage acceleration factor can be easily extended to include temperature dependency, and the effective activation energy derived from the power law is voltage dependent. Lastly, I studied the device characteristics of thin HfON charge-trap layer nonvolatile memory in a TaN/Al₂O₃/HfON/SiO₂/p-Si (TANOS) structure. A large memory window and fast erase speed, as well as good retention time, were achieved by using the NH₃ nitridation technique to incorporate nitrogen into the thin HfO₂ layer, which causes a high electron-trap density in the HfON layer. The higher dielectric constant of the HfON charge-trap layer induces a higher electric field in the tunneling oxide at the same voltage compared to non-nitrided films and, thus, creates a high Fowler-Nordheim (FN) tunneling current to increase the erase and programming speed. The trap-level energy in the HfON layer was calculated by using an amphoteric model. / text

The evolution of the MOSFET technology has been driven by the aggressive shrinkage of the device size to improve the device performance and to increase the circuit density. Currently, many research demonstrated that the continuous polycrystalline silicon film in the floating-gate dielectric could be replaced with nanocrystal (nc) embedded high-k thin film to minimize the charge loss due to the defective thin tunnel dielectric layer. This research deals with both the statistical aspect of reliability and electrical aspect of reliability characterization as well. In this study, the Zr-doped HfO2 (ZrHfO) high-k MOS capacitors, which separately contain the nanocrystalline zinc oxide (nc-ZnO), silicon (nc-Si), Indium Tin Oxide (nc-ITO) and ruthenium (nc-Ru) are studied on their memory properties, charge transportation mechanism, ramp-relax test, accelerated life tests, failure rate estimation and thermal effect on the above reliability properties. C-V hysteresis result show that the amount of charges trapped in nanocrystal embedded films is in the order of nc-ZnO>nc-Ru>nc-Si~nc-ITO, which might probably be influenced by the EOT of each sample. In addition, all the results show that the nc-ZnO embedded ZrHfO non-volatile memory capacitor has the best memory property and reliability. In this study, the optimal burn-in time for this kind of device has been also investigated with nonparametric Bayesian analysis. The results show the optimal burn-in period for nc-ZnO embedded high-k device is 5470s with the maximum one-year mission reliability.

An experimental and theoretical approach is taken to determine the effect of a heterojunction on the effective work function in a metal/high-? gate stack, the characteristics of aqueous hydrochloric acid cleaned (aq-HCl) GaN surface and the interface between GaN and Al2O3, HfO2 and GaON. The investigation of the effect of a heterojunction on the effective work function in a metal/high-? gate stack found that when a Ge/Si heterostructure on silicon is lightly doped and sufficiently thin, the work function can be extracted in a manner similar to that for a simple silicon substrate. Modifications to the terraced oxide structure are proposed to remove oxidation effects of the alternate channel materials. The extracted work function of TiN with various thicknesses on HfSiO is found to be in agreement with that of TiN on a silicon substrate. X-ray and ultraviolet photoelectron spectroscopy are used to observe the interface electronic states at the GaN (0001) and Al2O3, HfO2 and GaON dielectric interfaces. The GaN is cleaned using aqueous HCl prior to thermal oxidation to form GaON and atomic layer deposition of Al2O3 and HfO2. This was followed by a post deposition anneal. The GaN/HfO2 and GaN/Al2O3 interfaces exhibited dipoles of 1.6 eV and 0.4 eV +/- 0.2 eV, respectively. It is determined that the formation of an interfacial layer at the GaN/HfO2 interface is the primary cause of the larger dipole. Due to the knowledge of the formation of an interfacial GaOx or GaON layer during atomic layer deposition of HfO2, a better understanding of the GaN/GaON interface is needed. To accomplish this task, the interface electronic states at the GaN(0001) and GaON interface are observed using X-ray and ultraviolet photoelectron spectroscopy (XPS and UPS). XPS and UPS analysis of the GaN/GaON interface resulted in the calculation of a -2.7 eV +/- 0.2 eV dipole assuming that the core level shifts are only representative of the GaN band bending at the interface. If it is assumed that the core level shifts are only due to the oxidation of GaN, then the exhibited dipole at the GaN/GaON interface is -1.8 eV +/- 0.2 eV. Results indicate that the observed dipole is primarily caused by the polarization of the GaN. A theoretical approach is taken to provide a more complete understanding of the underlying formation mechanisms of a GaON interfacial layer during atomic layer deposition of HfO2. First, density functional theory is used to calculate the interactions of oxygen and water with the Ga-face of GaN clusters. The GaN clusters could be used as testbeds for the actual Ga-face on GaN crystals of importance in electronics. The results reveal that the local spin plays an important role in these interactions. It is found that the most stable interactions of O2 and the GaN clusters results in the complete dissociation of the O2 molecule to form two Ga-O-Ga bonds, while the most stable interactions between a H2O molecule and the GaN clusters are the complete dissociation of one of the O-H bonds to form a Ga-O-H bond and a Ga-H bond. Second, density functional theory is used to calculate the interaction of the reactants used to deposit HfO2 and Al2O3 during atomic layer deposition with hydrolyzed Ga-face GaN clusters. The results suggest that while further research is needed in this area to grasp a better understanding of the interactions of Trimethylaluminum (TMA) or Tertrakis(EthylMethylAmino)Hafnium (TEMAH) with hydrolyzed GaN clusters, it is found that a Ga-N(CH3)(CH2CH3) bond can form during the deposition of HfO2 using ALD and TEMAH as the reactant without breaking the Hf-N bond. The formation of a Ga-N(CH3)(CH2CH3) bond is significant because with the introduction of water into the system, the methyl and ethylmethyl groups may react to form a Ga-N-O bond which is believed to be the interfacial oxide found during deposition of HfO2 using ALD on GaN. No Ga-C bond structure formed in any fully optimized stable structure when analyzing the interaction of TMA with hydrolyzed GaN.

Zugl.: Aachen, Techn. Hochsch., Diss., 2007

Zugl.: Aachen, Techn. Hochsch., Diss., 2007

Zugl.: Aachen, Techn. Hochsch., Diss., 2007.

Zugl.: Cottbus, Techn. University, Diss., 2009.

abstract: High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use. In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

abstract: In this dissertation, in-situ X-ray and ultraviolet photoemission spectroscopy have been employed to study the interface chemistry and electronic structure of potential high-k gate stack materials. In these gate stack materials, HfO2 and La2O3 are selected as high-k dielectrics, VO2 and ZnO serve as potential channel layer materials. The gate stack structures have been prepared using a reactive electron beam system and a plasma enhanced atomic layer deposition system. Three interrelated issues represent the central themes of the research: 1) the interface band alignment, 2) candidate high-k materials, and 3) band bending, internal electric fields, and charge transfer. 1) The most highlighted issue is the band alignment of specific high-k structures. Band alignment relationships were deduced by analysis of XPS and UPS spectra for three different structures: a) HfO2/VO2/SiO2/Si, b) HfO2-La2O3/ZnO/SiO2/Si, and c) HfO2/VO2/ HfO2/SiO2/Si. The valence band offset of HfO2/VO2, ZnO/SiO2 and HfO2/SiO2 are determined to be 3.4 ± 0.1, 1.5 ± 0.1, and 0.7 ± 0.1 eV. The valence band offset between HfO2-La2O3 and ZnO was almost negligible. Two band alignment models, the electron affinity model and the charge neutrality level model, are discussed. The results show the charge neutrality model is preferred to describe these structures. 2) High-k candidate materials were studied through comparison of pure Hf oxide, pure La oxide, and alloyed Hf-La oxide films. An issue with the application of pure HfO2 is crystallization which may increase the leakage current in gate stack structures. An issue with the application of pure La2O3 is the presence of carbon contamination in the film. Our study shows that the alloyed Hf-La oxide films exhibit an amorphous structure along with reduced carbon contamination. 3) Band bending and internal electric fields in the gate stack structure were observed by XPS and UPS and indicate the charge transfer during the growth and process. The oxygen plasma may induce excess oxygen species with negative charges, which could be removed by He plasma treatment. The final HfO2 capping layer deposition may reduce the internal potential inside the structures. The band structure was approaching to a flat band condition. / Dissertation/Thesis / Ph.D. Physics 2012