Radio Frequency IDentification (RFID) Tags have become quite widespread in many services in the industry such as access control, parcel and document tracking, distribution logistics, automotive systems, and livestock or pet tracking. In these applications, a wireless communication link is provided between a remote transponder (antenna and integrated circuit (IC)) and an interrogator or reader. A suitable antenna for these tags must have low cost, low profile and especially small size whereas the bandwidth requirement (few kilohertz to megahertz) is less critical. In this document, methods to reduce tag size, the performance optimization of the tag by using novel antenna matching techniques for increased operational bandwidth and gain/radiation pattern/radiation efficiency improvement are introduced for 13.56 MHz HF and 915 MHz UHF RFID tags.In addition, an evaluation of an active 915 MHz UHF RFID field study for container tracking at the port of Savannah, GA is also presented.

The correlator is a key component of the digital backend of a modern radio telescope array. The 64 antenna MeerKAT telescope has an FX architecture correlator consisting of 64 F-Engines and 256 X-Engines. These F- and X-Engines are all hosted on 128 custom designed FPGA processing boards. This custom board is known as a SKARAB. One SKARAB X-Engine board hosts four logical X-Engines. This SKARAB ingests data at 27.2 Gbps over a 40 GbE connection. It correlates this data in real time. GPU technology has improved significantly since SKARAB was designed. GPUs are now becoming viable alternatives to FPGAs in high performance streaming applications. The objective of this dissertation is to investigate how to build a GPU drop-in replacement X-Engine for MeerKAT and to compare this implementation to a SKARAB X-Engine. This includes the construction and analysis of a prototype GPU X-Engine. The 40 GbE ingest, GPU correlation algorithm and the software pipeline framework that links these two together were identified as the three main sub-systems to focus on in this dissertation. A number of different tools implementing these sub-systems were examined with the most suitable ones being chosen for the prototype. A prototype dual socket system was built that could process the equivalent of two SKARABs worth of X-Engine data. This prototype has two 40 GbE Mellanox NICS running the SPEAD2 library and a single Nvidia GeForce 1080Ti GPU running the xGPU library. A custom pipeline framework built on top of the Intel Threaded Building Blocks (TBB) library was designed to facilitate the ow of data between these sub-systems. The prototype system was compared to two SKARABs. For an equivalent amount of processing, the GPU X-Engine cost R143 000 while the two SKARABs cost R490 000. The power consumption of the GPU X-Engine was more than twice that of the SKARABs (400W compared 180W), while only requiring half as much rack space. GPUs as X-Engines were found to be more suitable than FPGAs when cost and density are the main priorities. When power consumption is the priority, then FPGAs should be used. When running eight logical X-Engines, 85% of the prototype's CPU cores were used while only 75% of the GPU's compute capacity was utilised. The main bottleneck on the GPU X-Engine was on the CPU side of the server. This report suggests that the next iteration of the system should offload some CPU side processing to the GPU and double the number of 40 GbE ports. This could potentially double the system throughput. When considering methods to improve this system, an FPGA/GPU hybrid X-Engine concept was developed that would combine the power saving advantage of FPGAs and the low cost to compute ratio of GPUs.

Next generation optical networks will soon provide users the capability to request and obtain end-to-end all optical 10 Gbps channels on demand. Individual users will use these channels to exchange large amounts of data and support applications for scientific collaborative work. These new applications, which expect steady transfer rates in the order of Gbps, will very likely use either TCP or a new transport layer protocol as the end-to-end communication protocol. This thesis investigates the performance of TCP and newer TCP versions over High Bandwidth Delay Product Channels (HBDPC), such as the on demand optical channels described above. In addition, it investigates the performance of these new TCP versions over wireless networks and according to old issues such as fairness. This is particularly important to make adoption decisions. Using simulations, it is shown that 1) the window-based mechanism of current TCP implementations is not suitable to achieve high link utilization and 2) congestion control mechanisms, such as the one utilized by TCP Vegas and Westwood are more appropriate and provide better performance. Modifications to TCP Vegas and Scalable TCP are introduced to improve the performance of these versions over HBDPC. In addition, simulation results show that new TCP proposals for HBDPC, although they perform better than current TCP versions, still perform worse than TCP Vegas. Also, it was found that even though these newer versions improve TCP's performance over their original counterparts in HBDPC, they still have performance problems in wireless networks and present worse fairness problems than their old counterparts. The main conclusion of this thesis is that all these versions are still based on TCP's AIMD strategy or similar and therefore continue to be fairly blind in the way they increase and decrease their transmission rates. TCP will not be able to utilize the foreseen optical infrastructure adequately and support future applications if not redesigned to scale.

The main scope of this thesis is to implement a new architecture of a high bandwidth phase-locked loop (PLL) with a large operating frequency range from 100~MHz to 1~GHz in a 150~$nm$ CMOS process. As PLL is the time-discrete system, the new architecture is mathematically modelled in the z-domain. The charge pump provides a proportionally damped signal, which is unlikely as a resistive or capacitive damping used in the conventional charge pump. The new damping results in a less update jitter and less peaking to achieve the lock frequency and fast locking time of the PLL. The new semi-digital PLL architecture uses $N$ storage cells. The $N$ storage cells is used to store the oscillator tuning information digitally and also enables analogue tuning of the voltage controlled oscillator (VCO). The storage cells outputs are also used for the process voltage temperature compensation. The phase-frequency detector (PFD) and VCO are implemented like a conventional PLL. The bandwidth achieved is 1/4th of the PFD update frequency for all over the operating range from 100~MHz to 1~GHz. The simulation results are also verified with the mathematical modelling. The new architecture also consumes less power and area compared to the conventional PLL.

Capacitive Micromachined Ultrasonic Transducers (CMUTs) have been introduced as a viable alternative to piezoelectric transducers in medical ultrasound imaging in the last decade. CMUTs are especially suitable for applications requiring small size such as catheter based cardiovascular applications. Despite these advantages and their broad bandwidth, earlier studies indicated that the overall sensitivity of CMUTs need to be improved to match piezoelectric transducers. This dissertation addresses this issue by introducing the dual-electrode CMUT concept. Dual electrode configuration takes advantage of leveraged bending in electrostatic actuators to increase both the pressure output and receive sensitivity of the CMUTs. Static and dynamic finite element based models are developed to model the behavior of dual-electrode CMUTs. The devices are then successfully fabricated and characterized. Experiments illustrate that the pulse echo performance is increased by more than 15dB with dual-electrode CMUTs as compared to single electrode conventional CMUT. Further device optimization is explored via membrane shape adjustment by adding a center mass to the design. Electromechanical coupling coefficient (kc2) is investigated as a figure of merit to evaluate performance improvement with non-uniform/uniform membrane dual-electrode CMUTs. When the center mass is added to the design, the optimized non-uniform membrane increases the electromechanical coupling coefficient from 0.24 to 0.85 while increasing one-way 3dB fractional bandwidth from 80% to 140% and reducing the DC bias requirement from 160V to 132V. The results of this modeling study are successfully verified by experiments. With this membrane shape adjustment, significant performance improvement (nearly 20dB) is achieved with the dual-electrode CMUT structure that enables the CMUT performance to exceed that of piezoelectric transducers for many applications.

<p>A large volume of data is continuously being generated by data centers, humans, and the internet of things (IoT). In order to get useful insights, such enormous data must be processed in time with high throughput, low latency, and high accuracy. To meet such performance demands, a large body of new hardware is being shipped by vendors, such as multi-core CPUs, 3D-stacked memory, embedded microcontrollers, and other accelerators.</p><br><p>However, traditional operating systems (OSes) and data analytics frameworks, the key layer that bridges high-level data processing applications and low-level hardware, fails to deliver these requirements due to quickly evolving new hardware and increases in explosion of data. For instance, general OSes are not aware of the unique characters and demands of data processing applications. Data analytics engines for stream processing, e.g., Apache Spark and Beam, always add more machines to deal with more data but leave every single machine underutilized without fully exploiting underlying hardware features, which leads to poor efficiency. Data analytics frameworks for machine learning inference on IoT devices cannot run neural networks that exceed SRAM size, which disqualifies many important use cases.</p><br><p>In order to bridge the gap between the performance demands of data analytics and the new features of emerging hardware, in this thesis we exploit runtime system designs for high-level data processing applications by exploiting low-level modern hardware features. We study two important data analytics applications, including real-time stream processing and on-device machine learning inference, on three important hardware platforms across the Cloud and the Edge, including multicore CPUs, hybrid memory system combining 3D-stacked memory and general DRAM, and embedded microcontrollers with limited resources. </p><br><p>In order to speed up and enable the two data analytics applications on the three hardware platforms, this thesis contributes three related research projects. In project StreamBox, we exploit the parallelism and memory hierarchy of modern multicore hardware on single machines for stream processing, achieving scalable and highly efficient performance. In project StreamBox-HBM, we exploit hybrid memories to balance bandwidth and latency, achieving memory scalability and highly efficient performance. StreamBox and StreamBox-HBM both offer orders of magnitude performance improvements over the prior state of the art, opening up new applications with higher data processing needs. In project SwapNN, we investigate a system solution for microcontrollers (MCUs) to execute neural networks (NNs) inference out-of-core without losing accuracy, enabling new use cases and significantly expanding the scope of NN inference on tiny MCUs. </p><br><p>We report the system designs, system implementations, and experimental results. Based on our experience in building above systems, we provide general guidance on designing runtime systems across hardware/software stack for a wider range of new applications on future hardware platforms.</p><div><br></div>

Advances in transistor-integration technology and multi-core technology of the latest microprocessors have driven transient requirements to become more and more stringent. Rather than relying on the bulky output capacitors as energy-storage devices, increasing the control bandwidth (BW) of the multiphase voltage regulator (VR) is a more cost-effective and space-saving approach. However, it is found that the stability margin of current-mode control in high-BW design is very sensitive to operating conditions and component tolerance, depending on the performance of the current-sensing techniques, modulation schemes, and interleaving approaches. The primary objective of this dissertation is to investigate an advanced multiphase current-mode control, which provides accurate current sensing, enhances the stability margin in high-BW design, and adaptively compensates the parameter variations. Firstly, an equivalent circuit model for generic current-mode controls using DCR current sensing is developed to analyze the impact of component tolerance in high-BW design. Then, the existing state-of-the-art auto-tuning method used to improve current-sensing accuracy is reviewed, and the deficiency of using this method in a multiphase VR is identified. After that, enlightened by the proposed model, a novel auto-tuning method is proposed. This novel method features better tuning performance, noise-insensitivity, and simpler implementation than the state-of-the-art method. Secondly, the current state-of-the-art adaptive current-mode control based on constant-frequency PWM is reviewed, and its inability to maintain adequate stability margin in high-BW design is recognized. Therefore, a new external ramp compensation technique is proposed to keep the stability margin insensitive to the operating conditions and component tolerance, so the proposed high-BW constant-frequency control can meet the transient requirement without the presence of bulky output capacitors. The control scheme is generic and can be used in various kinds of constant-frequency controls, such as peak-current-mode, valley-current-mode, and average-current-mode configurations. Thirdly, an interleaving technique incorporating an adaptive PLL loop is presented, which enables the variable-frequency control to push the BW higher than proposed constant-frequency control, and avoids the beat-frequency input ripple. A generic small-signal model of the PLL loop is derived to investigate the stability issue caused by the parameter variations. Then, based on the proposed model, a simple adaptive control is developed to allow the BW of the PLL loop to be anchored at the highest phase margin. The adaptive PLL structure is applicable to different types of variable-frequency control, including constant on-time control and ramp pulse modulation. Fourthly, a hybrid interleaving structure is explored to simplify the implementation of the adaptive PLL structure in an application with more phases. It combines the adaptive PLL loop with a pulse-distribution technique to take the advantage of the high-BW design and fast transient response without adding a burden to the controller implementation. As a conclusion, based on the proposed analytical models, effective control concepts, systematic optimization strategies, viable implementations are fully investigated for high-BW current-mode control using different modulation techniques. Moreover, all the modeling results and the system performance are verified through simulation with a practical output filter model and an advanced mixed-signal experimental platform based on the latest MHz VR design on the laptop motherboard. In consequence, the multiphase VRs in future computation systems can be scalable easier with proposed multiphase configurations, increase the system reliability with proposed adaptive loop compensation, and minimize the total system footprint of the VR with the superior transient performance. / Ph. D.

High-bandwidth fuel modulation is currently one of the most promising methods for active combustion control. To attenuate the large pressure oscillations in the combustion chamber, the fuel is pulsed so that the heat release rate fluctuations damp the pressure oscillations in the combustor. This thesis focuses on the development and implementation of a high-bandwidth, proportional modulation system for liquid-fuel active combustion control. The throttle valve modulation system, discussed in this thesis, uses a 500-um piezoelectric stack coupled with an off-the-shelf valve. After comparing three other types of actuators, the piezoelectric stack was selected because of its compact size, bandwidth capabilities, and relatively low cost. Using the acoustic resonance of the fuel line, the system is able to achieve 128% pressure modulation, relative to the mean pressure, and is capable of producing more than 75% flow modulation at 115 Hz. Additionally, at 760 Hz the system produces 40% pressure modulation and 21% flow modulation with flow rates between 0.4 and 10 gph. Control authority was demonstrated on a single-nozzle kerosene combustor which exhibits a well-pronounced instability at ~115 Hz. Using the modulation system, the fundamental peak of the combustion instability was reduced by 30 dB, and the broadband sound pressure levels inside the combustor were reduced by 12 dB. However, the most important conclusion from the combustion control experiments was not the system?s accomplishments, but rather its inability to control the combustor at high global equivalence ratios. Our work indicates that having the ability to modulate a large percentage of the primary fuel is not always sufficient for active combustion control. / Master of Science

Classical Molecular Dynamics simulation (MD) models the interactions of thousands to millions of particles through the iterative application of basic Physics. MD is one of the core methods in High Performance Computing (HPC). While MD is critical to many high-profile applications, e.g. drug discovery and design, it suffers from the strong scaling problem, that is, while large computer systems can efficiently model large ensembles of particles, it is extremely challenging for {\it any} computer system to increase the timescale, even for small ensembles. This strong scaling problem can be mitigated with low-latency, direct communication. Of all Commercial Off the Shelf (COTS) Integrated Circuits (ICs), Field Programmable Gate Arrays (FPGAs) are the computational component uniquely applicable here: they have unmatched parallel communication capability both within the chip and externally to couple clusters of FPGAs. This thesis focuses on the acceleration of the long range (LR) force, the part of MD most difficult to scale, by using FPGAs. This thesis first optimizes LR acceleration on a single-FPGA to eliminate the amount of on-chip communication required to complete a single LR computation iteration while maintaining as much parallelism as possible. This is achieved by designing around application specific memory architectures. Doing so introduces data movement issues overcome by pipelined, toroidal-shift multiplexing (MUXing) and pipelined staggering of memory access subsets. This design is then evaluated comprehensively and comparatively, deriving equations for performance and resource consumption and drawing metrics from previously developed LR hardware designs. Using this single-FPGA LR architecture as a base, FPGA network strategies to compute the LR portion of larger sized MD problems are then theorized and analyzed.

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