Title from second page of PDF document. Includes bibliographical references.

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 111-113). Also available in electronic format on the Internet.

Thesis (M. Eng.)--Carleton University, 1993. / Also available in electronic format on the Internet.

Thesis (Ph. D.)--Florida State University, 2005. / Advisor: Dr. Christopher K. W. Tam, Florida State University, College of Arts and Sciences, Dept. of Mathematics. Title and description from dissertation home page (viewed Sept. 21, 2005). Document formatted into pages; contains xv, 118 pages. Includes bibliographical references.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007. / Cressler, John, Committee Chair ; Laskar, Joy, Committee Member ; Papapolymerou, Ioannis, Committee Member ; Zhou, Haomin, Committee Member ; Milor, Linda, Committee Member.

Thesis (B.S.) Magna Cum Laude--Butler University, 2007. / Includes bibliographical references (leaves 26-27).

A lateral jet in a supersonic crossflow creates a highly complex three-dimensional flow field which is not easily predicted. The aim of this research was to assess the use of a RANS based CFD method to simulate a lateral jet in supersonic crossflow interaction by comparing the performance of available RANS turbulence models. Four turbulence models were trialled in increasingly complex configurations; a flat plate, a body of revolution and a body of revolution at incidence. The results of this numerical campaign were compared to existing experimental and numerical data. Overall the Spalart-Allmaras turbulence model provided the best fit to experimental data. The performance of the lateral jet as a reaction control system was assed by calculating the force and moment amplification factors. The predicted flowfield surrounding the interaction was analysed in detail and was shown to predict the accepted shock and vortical structures. The lateral jet interaction flowfield over a body of revolution was shown to be qualitatively the same as that over a flat plate. An experimental facility was designed and manufactured allowing the study of the lateral jet interaction in Cranfield University’s 2 ½” x 2 ½” supersonic windtunnel. The interaction was studied with a freestream Mach number of 1.8, 2.4 & 3.1 and over a range of pressure ratios (50≤PR≤200). Levels of unsteadiness in the interaction were measured using high bandwidth pressure transducers. The level of unsteadiness was quantified by calculating the OASPL of the pressure signal. OASPL was found to increase with increasing levels of PR or MPR and to decrease with increases of Mach number. The levels of unsteadiness found were low with the highest levels found downstream of the jet.

Made available in DSpace on 2014-06-11T19:27:13Z (GMT). No. of bitstreams: 0 Previous issue date: 2010-02-26Bitstream added on 2014-06-13T19:55:30Z : No. of bitstreams: 1 rigatti_amy_me_ilha.pdf: 2241422 bytes, checksum: 8c8e195352a6068cd9086572b3723f9f (MD5) / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / Este trabalho apresenta um estudo sobre a influência das condições de fresamento na força de usinagem e na energia específica de corte. Foram ensaiados dois tipos de materiais que sofreram diferentes formas de tratamentos térmicos. O aço CL 23 (Eaton Ltda) foi normalizado, resfriado ao forno e resfriado ao ar, e o aço COS AR 60 (Usiminas S/A) foi empregado na condição “como recebido” e tratado termomecanicamente, onde a microestrutura foi refinada a 1,7 m. Para o primeiro material, empregou-se 3 condições de usinagem, com parâmetros de corte fixos e distintos entre si, e para o segundo material, foram utilizadas 8 condições, em que todos os parâmetros variaram visando à aplicação da Análise de Variância (ANOVA). Os ensaios de fresamento de topo concordante a seco foram conduzidos em um centro de usinagem CNC de 11 kW de potência e rotação do eixo-árvore de 7.500 rpm. Empregou-se ferramenta de diâmetro 25 mm com dois insertos de metal duro revestidos com TiN e TiNAl. A força de usinagem foi obtida utilizando-se um dinamômetro piezelétrico de 3 componentes e sistema de aquisição, cujos sinais foram pós-processados para o cálculo da força de usinagem máxima, força de usinagem RMS e energia específica de corte. Os resultados apontam para uma influência da condição de usinagem sobre a força de usinagem e energia específica de corte. A condição com alta velocidade de corte (HSC - High-Speed Cutting) apresentou menores forças de usinagem e maiores energias específicas de corte. A usinagem assumida como convencional, apresentou maiores níveis de força de usinagem e energia específica menores. A força de usinagem se mostrou estatisticamente dependente da profundidade de usinagem e a energia específica do avanço da ferramenta. A velocidade de corte influiu de forma significativa na força de usinagem e na energia específica de corte... / This research deals with the influence of milling conditions on machining force and specific cutting energy. Two kind of workpiece materials thermally treated were used on tests. CL23 carbon steel (Eaton Ltda) was normalized, furnace cooled and air cooled and COS AR 60 carbon steel (Usiminas S/A) was employed in “as received” and refined grains (1.7 m) conditions. For the first material, three machining conditions were applied with constant and different cutting parameters. For the second steel, eight machining conditions were implemented where all cutting parameters varied aiming at application of Variance Analysis (ANOVA). The machining tests were carried out by using dry end milling under down milling strategy in a CNC machining center with 11 kW power and 7,500 rpm spindle speed. A 25 mm diameter endmill with two inserts (TiN and TiNAl coatings) was used. The machining force was measured by means of 3-components piezoelectric dynamometer and acquisition system, whose signals were post-processed in order to calculate the maximum machining force, RMS machining force and specific cutting energy. The results show the cutting condition influences on all researched variables. High-speed cutting (HSC) decreased the machining force and increased the specific cutting energy. The milling named conventional condition elevated the machining force and diminished the specific cutting energy. The depth of cut was statistically influent on machining force and the feed per tooth was determinant for specific cutting energy. The cutting speed influenced significantly on machining force and specific cutting energy. Microstructural condition of workpiece material demonstrated to be important over studied variables only when hardness values were different significantly. The results of specific cutting energy from this work present good correlation with those obtained from theoretical models proposed by Taylor, Kienzle, ASME, AWF and Sandvik

Grace à leur simplicité de routage, la réduction du bruit, de la consommation d'energie, d'espace de routage et d'interférences électromagnétiques en comparaison avec les liaisons parallèles, les Liaisons Série Haut Débit (High-Speed Serial Links) se trouvent aujourd'hui dans la grande majorité des systèmes sur puce (SoC) connectant les différents composants : la puce principale avec ses entrées/sorties, la puce principale avec une autre puce, la communication inter-processeurs etc…Par contre, changer des liaisons parallèles pour utiliser des liaisons séries haut débit présente plusieurs défi : les liaisons série haut débit doivent tourner à des fréquences plus élevées que celle des liaisons parallèles pour atteindre plusieurs Gigabits par seconde (Gbps) pour garder le même débit que celui des liaisons parallèles, tout en répondant à l'augmentation exponentielle de la demande de débit. L'atténuation du signal sur le cuivre augmente avec la fréquence, nécessitant de plus en plus d'égaliseurs et de techniques de filtrage, et donc augmentant la complexité du design et la consommation d'énergie.L'une des façons pour optimiser le design avec des hautes fréquences c'est d'intégrer l'horloge dans la ligne de données, car une ligne d'horloge implique plus de surface de routage et elle pourra bien devenir une source d'interférences électromagnétiques (EMI). Une autre bonne raison pour utiliser une horloge intégrée c'est que la déviation du signal d'horloge par rapport au signal de data (skew en anglais) devient difficile à contrôler sur des fréquences élevées. Des transitions doivent donc être assurées dans les données transmises, pour que le récepteur soit capable de se synchroniser et de récupérer les données correctement. En d'autres termes, le nombre de bits consécutifs, aussi appelé la Run Length (RL) en anglais doit être réduit ou borné à une certaine limite.Un autre défi ou caractéristique à réduire ou borner dans les données à transmettre est la différence entre le nombre de bits à 1 et le nombre de bits à 0 transmis. On l'appelle la disparité RD (de l'anglais Running Disparity). Les grands écarts entre le nombre de bits à 1 et les bits à 0 transférés peuvent provoquer un décalage du signal par rapport à la ligne de base. On appelle ça le Baseline Wander en anglais (BLW). Le BLW pourra augmenter le taux de bits erronés (Bit Error Rate – BER) ou exiger des techniques de filtrage et d'égalisations au récepteur pour être corrigé. Cela va donc augmenter la complexité du design et la consommation d'énergie.Pour assurer une RL et une RD bornées, les données à transmettre sont généralement encodés. A travers le temps, plusieurs méthodes d'encodages ont été présentées et utilisées dans les standards ; certaines présentent de très bonnes caractéristiques mais au cout d'un grand nombre supplémentaire de bits, en anglais appelé Overhead, affectant donc le débit. D'autres encodages ont un overhead moins important mais n'assurent pas les mêmes limites de RL et de RD, et par conséquence ils nécessitent plus de complexité analogique pour corriger les conséquences et donc augmentant ainsi la consommation d'énergie.Dans cette thèse, on propose un nouvel encodage de données qui peut borner la RD et la RL pour les bornes souhaités, et avec un très faible cout sur la bande passante (l'overhead). Ce codage permet de borner la RL et la RD aux mêmes limites que les autres codages et avec un overhead 10 fois moins important.Dans un premier temps on montre comment on peut borner la RL à la valeur souhaitée avec un codage à très faible overhead. Dans un second temps on propose un encodage très faible cout pour borner la RD à la valeur souhaitée aussi. Ensuite on montrera comment on pourra fusionner ces deux encodages en un seul, pour construire un encodage de données programmable et à faible cout de bande passante, limité en disparité et en nombre de bits identiques consécutifs. / Thanks to their routing simplicity, noise, EMI (Electro-Magnetic Interferences), area and power consumption reduction advantages over parallel links, High Speed Serial Links (HSSLs) are found in almost all today's System-on-Chip (SoC) connecting different components: the main chip to its Inputs/Outputs (I/Os), the main chip to a companion chip, Inter-Processor Communication (IPC) and etc… Serial memory might even be the successor of current DDR memories.However, going from parallel links to high-speed serial links presents many challenges; HSSLs must run at higher speeds reaching many gigabits per second to maintain the same end-to-end throughput as parallel links as well as satisfying the exponential increase in the demand for throughput. The signal's attenuation over copper increases with the frequency, requiring more equalizers and filtering techniques, thereby increasing the design complexity and the power consumption.One way to optimize the design at high speeds is to embed the clock within the data, because a clock line means more routing surface, and it also can be source to high EMI. Another good reason to use an embedded clock is that the skew (time mismatch between the clock and the data lanes) becomes hard to control at high frequencies. Transitions must then be ensured inside the data that is sent on the line, for the receiver to be able to synchronize and recover the data correctly. In other words, the number of Consecutive Identical Bits (CIBs) also called the Run Length (RL) must be reduced or bounded to a certain limit.Another challenge and characteristic that must be bounded or reduced in the data to send on a HSSL is the difference between the number of ‘0' bits and ‘1' bits. It is called the Running Disparity (RD). Big differences between 1's and 0's could shift the signal from the reference line. This phenomenon is known as Base-Line Wander (BLW) that could increase the BER (Bit Error Rate) and require filtering or equalizing techniques to be corrected at the receiver, increasing its complexity and power consumption.In order to ensure a bounded Run Length and Running Disparity, the data to be transmitted is generally encoded. The encoding procedure is also called line coding. Over time, many encoding methods were presented and used in the standards; some present very good characteristics but at the cost of high additional bits, also called bandwidth overhead, others have low or no overhead but do not ensure the same RL and RD bounds, thus requiring more analog design complexity and increasing the power consumption.In this thesis, we propose a novel programmable line coding that can perform to the desired RL and RD bounds with a very low overhead, down to 10 times lower that the existing used encodings and for the same bounds. First, we show how we can obtain a very low overhead RL limited line coding, and second we propose a very low overhead method which bounds the RD, and then we show how we can combine both techniques in order to build a low overhead, Run Length Limited, and Running Disparity bounded Line Coding

Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both CS capacitor array and the latch comparator during ADC operations. The impacts of the proposed techniques on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The dissertation also presents techniques to cope with capacitor mismatches, which becomes more significant with the use of very small unit capacitors in the CS array. These techniques rely on a novel programmable CS capacitor array that allow optimally grouping the unit capacitors. Based on a 0.13um CMOS technology the proposed techniques are verified with extensive circuit simulation. Post layout simulations are done to evaluate the proposed techniques for energy efficient CS capacitor array.