Community Wireless Networks (CWNs) are a fairly new phenomenon. One of the first projects, NYC Wireless, started in 2001. These wireless initiatives are often a response to the lack of high-speed ubiquitous computing. Many of the first users, frustrated neighborhood “techies,” jerry rigged low cost WiFi antennas to rooftops and the side of buildings in order to access a high-speed broadband service. By doing this the wireless pioneers shared high speed wireless signals with neighbors and anyone within reach of their signal. As wireless computing became more popular, and it’s social and economic benefits more obvious, CWNs became an attractive alternative for many rural and low-income urban communities. Populations that had been overlooked by large cable and telephone service companies. The success of CWNs has paved the way for municipalities to build publicly supported wireless projects. Cable and telephone companies, major providers of broadband service, view municipal networks as unfair competition, and thus began the legislative battle over municipal wireless networks. The battle continues to wage. Cable and telephone companies have had some success at the state level and the federal debate is underway at this moment. Therefore, the purpose of this report is to understand the role Austin’s nonprofits play to ensure that high speed broadband access is made available for everyone and how lessons learned in Austin can be applied to other cities and locations around the country. The study found that Austin, compared to other cities of the same size, has a very small nonprofit community to addresses the issue of universal broadband access. Although the group is small, networking and mingling between community service organizations, the city government and wireless projects has created a community that effectively addresses the issue of high-speed access to the Internet. / text

published_or_final_version / Transport Policy and Planning / Master / Master of Arts in Transport Policy and Planning

Most used security mechanisms in high-speed networks have been adopted without adequate quantification of their impact on performance degradation. Appropriate quantitative network models may be employed for the evaluation and prediction of 'optimal' performance vs. security trade-offs. Several quantitative models introduced in the literature are based on queueing networks (QNs) and generalised stochastic Petri nets (GSPNs). However, these models do not take into consideration Performance Engineering Principles (PEPs) and the adverse impact of traffic burstiness and security protocols on performance. The contributions of this thesis are based on the development of an effective quantitative methodology for the analysis of arbitrary QN models and GSPNs through discrete-event simulation (DES) and extended applications into performance vs. security trade-offs involving infrastructure and infrastructure-less high-speed networks under bursty traffic conditions. Specifically, investigations are carried out focusing, for illustration purposes, on high-speed network routers subject to Access Control List (ACL) and also Robotic Ad Hoc Networks (RANETs) with Wired Equivalent Privacy (WEP) and Selective Security (SS) protocols, respectively. The Generalised Exponential (GE) distribution is used to model inter-arrival and service times at each node in order to capture the traffic burstiness of the network and predict pessimistic 'upper bounds' of network performance. In the context of a router with ACL mechanism representing an infrastructure network node, performance degradation is caused due to high-speed incoming traffic in conjunction with ACL security computations making the router a bottleneck in the network. To quantify and predict the trade-off of this degradation, the proposed quantitative methodology employs a suitable QN model consisting of two queues connected in a tandem configuration. These queues have single or quad-core CPUs with multiple-classes and correspond to a security processing node and a transmission forwarding node. First-Come-First-Served (FCFS) and Head-of-the-Line (HoL) are the adopted service disciplines together with Complete Buffer Sharing (CBS) and Partial Buffer Sharing (PBS) buffer management schemes. The mean response time and packet loss probability at each queue are employed as typical performance metrics. Numerical experiments are carried out, based on DES, in order to establish a balanced trade-off between security and performance towards the design and development of efficient router architectures under bursty traffic conditions. The proposed methodology is also applied into the evaluation of performance vs. security trade-offs of robotic ad hoc networks (RANETs) with mobility subject to Wired Equivalent Privacy (WEP) and Selective Security (SS) protocols. WEP protocol is engaged to provide confidentiality and integrity to exchanged data amongst robotic nodes of a RANET and thus, to prevent data capturing by unauthorised users. WEP security mechanisms in RANETs, as infrastructure-less networks, are performed at each individual robotic node subject to traffic burstiness as well as nodal mobility. In this context, the proposed quantitative methodology is extended to incorporate an open QN model of a RANET with Gated queues (G-Queues), arbitrary topology and multiple classes of data packets with FCFS and HoL disciplines under bursty arrival traffic flows characterised by an Interrupted Compound Poisson Process (ICPP). SS is included in the Gated-QN (G-QN) model in order to establish an 'optimal' performance vs. security trade-off. For this purpose, PEPs, such as the provision of multiple classes with HoL priorities and the availability of dual CPUs, are complemented by the inclusion of robot's mobility, enabling realistic decisions in mitigating the performance of mobile robotic nodes in the presence of security. The mean marginal end-to-end delay was adopted as the performance metric that gives indication on the security improvement. The proposed quantitative methodology is further enhanced by formulating an advanced hybrid framework for capturing 'optimal' performance vs. security trade-offs for each node of a RANET by taking more explicitly into consideration security control and battery life. Specifically, each robotic node is represented by a hybrid Gated GSPN (G-GSPN) and a QN model. In this context, the G-GSPN incorporates bursty multiple class traffic flows, nodal mobility, security processing and control whilst the QN model has, generally, an arbitrary configuration with finite capacity channel queues reflecting 'intra'-robot (component-to-component) communication and 'inter'-robot transmissions. Two theoretical case studies from the literature are adapted to illustrate the utility of the QN towards modelling 'intra' and 'inter' robot communications. Extensions of the combined performance and security metrics (CPSMs) proposed in the literature are suggested to facilitate investigating and optimising RANET's performance vs. security trade-offs. This framework has a promising potential modelling more meaningfully and explicitly the behaviour of security processing and control mechanisms as well as capturing the robot's heterogeneity (in terms of the robot architecture and application/task context) in the near future (c.f. [1]. Moreover, this framework should enable testing robot's configurations during design and development stages of RANETs as well as modifying and tuning existing configurations of RANETs towards enhanced 'optimal' performance and security trade-offs.

The objective of this dissertation is to study the switched reluctance machine (SRM) electromagnetic design and optimization. The research of electric machines is mostly driven by the motivation for higher efficiency and lower cost. The demands for high-performance electric machines also come from the development of emerging industries, such as electric vehicles (EV), hybrid electric vehicles (HEV), renewable energy conversion, energy storage and precision manufacturing. The additional requirements for those applications include volume, weight, speed, torque, reliability, fault tolerance capability, etc. The focus of the research effort is on the high speed and high torque applications, where the SRM stands out compared to other types of machines. The conventional design method significantly depends on the designer’s experience, which uses equivalent magnetic circuit models, and therefore the SRM design is not well developed. A novel SRM electromagnetic design and optimization method is developed, which uses the current-fed FEA simulation as the SRM performance estimation tool. This method serves as the main innovation of this research work. First, the proposed method is applicable to any SRM topologies and dimension, and no detailed modeling of a specific SRM configuration is required in advance. Therefore, an automated SRM design and optimization approach is developed. Secondly, great accuracy of the SRM electromagnetic analysis, e.g. flux density, torque, and current calculation, is achieved by using FEA simulation instead of simplified magnetic circuit approximations. This contribution is particularly significant when considering the poor accuracy of conventional SRM analytical analysis methods, where several assumptions and approximations are used. Lastly, the proposed design method takes the typical SRM control strategy into account, where the excitation current profile is characterized as a trapezoid. This method adapts the flux linkage of the first FEA simulation result to specify the excitation current profile for the second FEA simulation, so the calculated SRM performance in FEA simulation agrees with the measurement on a practical machine. The proposed SRM design and optimization method is used for a 12/8 SRM rotor design and for a complete 4/2 SRM design. These design examples validate the applicability of the proposed method to different SRM configurations and dimensions. Detailed design steps are presented for both design cases, and the selection of the parametric design variables are also discussed. The optimization results are demonstrated using multi-dimension diagrams, where the optimal design with the highest torque can be easily identified. The FEA simulation results are compared to the experimental results of a fabricated SRM prototype, and good agreement is found. In addition, a new rotor configuration with a flux bridge is proposed for an ultra high speed SRM design. The primary motivation of this rotor topology is to reduce the windgae losses and the acoustic noise at a high speed of 50,000 rpm. However, care must be taken for the flux bridge design, and the impact of different flux bridge thicknesses to the SRM performance is studied. Meanwhile, the manufacturing difficulties and the mechanical stresses should also be considered when fabricating the flux-bridge rotor. As a result, two SRM prototypes are built, and the two rotors are one without a flux bridge and one with a flux bridge. The prototypes are tested at different speeds (10,000 rpm, 20,000 rpm and 50,000 rpm) respectively, and the experimental results show good agreement with the FEA simulation results.

In this thesis we discuss the design and implementation of Digital Signal Processing (DSP) applications in a standard digital CMOS technology. The aim is to fulfill a throughput requirement with lowest possible power consumption. As a case study a frequency selective filter is implemented using a half-band FIR filter and a bireciprocal Lattice Wave Digital Filter (LWDF) in a 0.35 µm CMOS process. The thesis is presented in a top-down manner, following the steps in the topdown design methodology. This design methodology, which has been used for bit-serial maximally fast implementations of IIR filters in the past, is here extended and applied for digit-serial implementations of recursive and non-recursive algorithms. Transformations such as pipelining and unfolding for increasing the throughput is applied and compared from throughput and power consumption points of view. A measure of the level of the logic pipelining is developed, i.e., the Latency Model (LM), which is used as a tuning variable between throughput and power consumption. The excess speed gained by the transformations can later be traded for low power operation by lowering the supply voltage, i.e., architecture driven voltage scaling. In the FIR filter case, it is shown that for low power operation with a given throughput requirement, that algorithm unfolding without pipelining is preferable. Decreasing the power consumption with 40, and 50 percent compared to pipelining at the logic or algorithm level, respectively. The digit-size should be tuned with the throughput requirement, i.e., using a large digit-size for low throughput requirement and decrease the digit-size with increasing throughput. In the bireciprocal LWDF case, the LM order can be used as a tuning variable for a trade-off between low energy consumption and high throughput. In this case using LM 0, i.e., non-pipelined processing elements yields minimum energy consumption and LM 1, i.e., use of pipelined processing elements, yields maximum throughput. By introducing some pipelined processing elements in the non-pipelined filter design a fractional LM order is obtained. Using three adders between every pipeline register, i.e., LM 1/3, yields a near maximum throughput and a near minimum energy consumption. In all cases should the digit-size be equal to the number of fractional bits in the coefficient. At the arithmetic level, digit-serial adders is designed and implemented in a 0.35 µm CMOS process, showing that for the digit-sizes, , the Ripple-Carry Adders (RCA) are preferable over Carry-Look-Ahead adders (CLA) from a throughput point of view. It is also shown that fixed coefficient digitserial multipliers based on unfolding of serial/parallel multipliers can obtain the same throughput as the corresponding adder in the digit-size range D = 2...4. A complex multiplier based on distributed arithmetic is used as a test case, implemented in a 0.8 µm CMOS process for evaluation of different logic styles from robustness, area, speed, and power consumption points of view. The evaluated logic styles are, non-overlapping pseudo two-phase clocked C2MOS latches with pass-transistor logic, Precharged True Single Phase Clocked logic (PTSPC), and Differential Cascade Voltage Switch logic (DCVS) with Single Transistor Clocked (STC) latches. In addition we propose a non-precharged true single phase clocked differential logic style, which is suitable for implementation of robust, high speed, and low power arithmetic processing elements, denoted Differential NMOS logic (DN-logic). The comparison shows that the two-phase clocked logic style is the best choice from a power consumption point of view, when voltage scaling can not be applied and the throughput requirement is low. However, the DN-logic style is the best choice when the throughput requirements is high or when voltage scaling is used.

The United States as a whole is embarking on the historic task of implementing high-speed rail (HSR) throughout the country in an attempt to improve regional mobility, including congestion at some of the nation’s busiest airports. However, despite the wide overlapping of service that both air and HSR provide and the goal of reducing airport congestion, little discourse has occurred on the topic of how these two modes might interact in an intermodal context. This report explores how air travel and HSR might cooperate in the US, which is defined as an explicit attempt by the two modes to utilize each other in order to transport a passenger to their final destination. It will document potential benefits of cooperation, survey how cooperation works elsewhere in the world, and investigate the current climate within the US for cooperation, including a review of current HSR plans and analysis of air travel data. This information will form the basis for suggested airports for the integration of HSR and air travel, and for how US airlines might utilize HSR. Lastly, lessons learned will form a list of best practices to follow in order to better insure a cooperative and successful relationship between HSR and air travel. / text

Current transportation methods within the Central Arizona region revolve primarily around automobiles. In order for the region to become more economically resilient and environmentally sustainable, alternative transportation methods must be considered. One such alternative that has shown great promise in other regions of the United States is rail transport. Rail transport, including commuter rail or high speed rail, has proven to not only be an effective alternative to automobile transport, but also as a more environmentally sustainable transportation option. The I-11 Super Corridor study, a part of the University of Arizona’s Sustainable City Project 2014, applied next generation urban planning design ideas to the planned Interstate 11 corridor, a major transportation artery that will connect Mexico and Canada. This study inspired this project’s focus on the concept of identifying suitable routes for new transportation infrastructure within the central and southern Arizona regions. Through the incorporation of commuter or high speed rail within central and southern Arizona, a more resilient regional economy and environment can be created. The previous I-11 Super Corridor study presented the incorporation of different regional factors, including population density and economic statistics, to determine suitable routes for future transportation corridors. This project integrates the utilization of specific local and regional data and advanced GIS analysis to determine suitable routes for new rail transport corridors within Maricopa, Pinal and Pima Counties.

To ATM είναι μια δικτυακή τεχνολογία μετάδοσης που υποστηρίζει την μεταφορά ετερογενούς κίνησης, δηλ πραγματικού χρόνου όπως ήχος, εικόνα και μη πραγματικού χρόνου όπως υπολογιστικά δεδομένα, χρησιμοποιώντας έναν μηχανισμό που διαβιβάζει μονάδες δεδομένων σταθερού μεγέθους, τα cells. Η απόδοση του δικτύου ΑΤΜ εξαρτάται σε μεγάλο βαθμό από την χαρακτηριστικά των μεταγωγέων πακέτων. Για την ανάπτυξη αποτελεσματικών μεταγωγέων χρειάζεται να αναπτύξουμε αποτελεσματικούς χρονοπρογραμματιστές υψηλής ταχύτητας που είναι απλοί στην υλοποίησή τους. Στα πλαίσια αυτής της μεταπτυχιακής εργασίας γίνεται η μελέτη και η υλοποίηση ενός νέου κατανεμημένου αλγορίθμου χρονοπρογραμματισμού για μεταγωγέα ΑΤΜ, που χρησιμοποιεί μνήμη οργανωμένη σε πολλαπλές ουρές εισόδου για την αποθήκευση των πακέτων πριν την δρομολόγησή τους. O αλγόριθμος Αμοιβαίας Προτεραιότητας (Mutual Priority) μπορεί να επιτύχει υψηλό throughput και βέλτιστη εγγύηση εξυπηρέτησης, ίση με Ν κύκλους. Επιπλέον προσφέρει πολύ υψηλή απόδοση ακόμα και με μια μόνο επανάληψη, υπερτερώντας έτσι των υπόλοιπων αλγορίθμων. Η υλοποίησηση του αλγορίθμου Αμοιβαίας Προτεραιότητας εκτελείται με 2 τρόπους: α) σε υλικό (FPGA) και β) σε λογισμικό (κώδικας C για AVR). Η πλατφόρμα FPSLIC μας επιτρέπει να αξιολογήσουμε και να συγκρίνουμε τις hardware και software υλοποιήσεις του αλγορίθμου κατά έναν ρεαλιστικό τρόπο, αφού τόσο ο μικροελεγκτής ΑVR, αλλά και η προγραμματιζόμενη λογική FPGA είναι κατασκευασμένα με την ίδια ακριβώς τεχνολογία, ενσωματωμένα σε μια μονολιθική συσκευή. Τέλος εξάγουμε αποτελέσματα μετρήσεων της ταχύτητας και επιφάνειας του χρονοπρογραμματιστή και εκπονούμε σύγκριση για διαφορετικά μεγέθη μεταγωγέα στην απόδοση μεταξύ των 2 υλοποιήσεων του αλγορίθμου μεταξύ τους, αλλά και σύγκριση μεταξύ αποτελεσμάτων, που έχουν ληφθεί από παρεμφερή εργασία, του αλγορίθμου FIRM και του αλγόριθμου Mutual Priority. Παρατηρούμε ότι ο αλγόριθμος Mutual Priority υπερέχει ξεκάθαρα, είτε για υλοποίηση σε υλικό είτε σε λογισμικό, έναντι του άλλου αλγορίθμου. / ATM is a network transmission technology that allows transfer of heterogeneous traffic, that is real-time like sound, image and non real-time like computer data, using a mechanism that delivers fixed size data units, the cells. The performance-efficiency of ATM network depends on a grate scale from the characteristics of packet switches. In order to develop efficient switches we need to design optimal high speed schedulers, which are easy to realize. In this master thesis, we present the study and realization of a new distributed scheduling algorithm for ATM switch, that uses memory organized according to the scheme of advanced input queuing. Mutual Priority Scheduler can achieve high throughput and optimum service guarentee, equal to N cycles. Furthermore it provides high performance, even with one iteration, exceeding all the other algoritms. The realization of the algorithm is performed with 2 ways: a)in hardware and b) in software. Fpslic platform let us evaluate and compare these 2 different realizations of Mutual Priority algorithm, as it contains an FPGA and a microcontroller embedded on the same chip. Finaly we present measurements for the speed and area of the scheduler, and make comparisons for different switch sizes. Moreover we compare the realization of Mutual Priority Scheduler and that of Firm scheduler. We take us an outcome that Mutual Priority scheduler surpass the other algorithm either in hardware, or in software.

This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V. The comparator is designed for time-interleaved bandpass sigma-delta ADC. Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less than half the clock cycle which means it does not effect the functionality of the bandpass sigma-delta ADC in terms of speed. The simulation results are derived using Cadence environment. The results show that the comparator has 6-bit resolution and power consumption of 4.13 mW for the worst-case frequency of 250 MHz. It fulfills all the performance requirements, most of them with large margins.

The internet revolution has led to the demand for high speed, low cost solutions for providing high bandwidth to the consumers. Cable and DSL systems address these requirements through sophisticated analog and digital signal processing schemes. A key element of the analog front end of such systems is the line driver which interfaces with the transmission medium such as co-axial cable or twisted pair. The line driver is an amplifier that provides the necessary output current to drive the low impedance of the line. The main requirements for design are high output swing, high linearity, matched impedance to the line and power efficiency. These requirements are addressed by a class AB amplifier whose output impedance can be controlled through feedback. The property of this topology is that when the gain is unity, the output resistance of the driver is matched to the line resistance. Unity gain is achieved for varying line conditions through a tuning loop consisting of peak-to-peak detectors and differential difference amplifier. The design is fabricated in 0.5 micron AMI CMOS process technology. For line variations from 65 to 170 ohms, the gain is unity with an error of 3 % and the impedance matching error is 20 % at the worst-case. The linearity is better than 50 dB for a 1.2 V peak-to-peak signal over the signal bandwidth from 10 kHz to 5 MHz and the line resitance range from 65 to 160 ohms.