As CMOS device sizes shrink, the channel electric field becomes higher and the hot carrier (HC) effect becomes more significant. When the oxide is scaled down to less than 3 nm, gate oxide breakdown (BD) often takes place. As a result, oxide trapping and interface generation cause long term performance drift and related reliability problems in devices and circuits. The RF front-end circuits include low noise amplifier (LNA), local oscillator (LO) and mixer. It is desirable for a LNA to achieve high gain with low noise figure, a LO to generate low noise signal with sufficient output power, wide tuning range, and high stability, and a mixer to up-convert or down-convert the signal with good linearity. However, the RF front-end circuit performance is very sensitive to the variation of device parameters. The experimental results show that device performance is degraded significantly subject to HC stress and BD. Therefore, RF front-end performance is degraded by HC and BD effects. With scaling and increasing chip power dissipation, operating temperatures for device have also been increasing. Another reliability concern, which is the negative bias temperature instability (NBTI) caused by the interface traps under high temperature and negative gate voltage bias, arises when the operation temperature of devices increases. NBTI has received much attention in recent year and it is found that NIT is present for all stress conditions and NOT is found to occur at high VG. Therefore, the probability of BD in pMOSFET increases with temperature since trapped charges during the NBTI process increase, thus resulting in percolation, a main cause of oxide degradation. The above effects can cause significant degradations in transistors, thus leading to the shifts of RF performance. This dissertation focuses on the following aspects: (1) RF performance degradation in nMOSFET and pMOSFET due to hot carrier and soft breakdown effects are examined experimentally and will be used for circuit application in the future. (2) A modeling method to analyze the gate oxide breakdown effects on RF nMOSFET has been proposed. The device performance drifts due to gate oxide breakdown are examined, breakdown spot resistance and total gate capacitance are extracted before and after stress for 0.16 um CMOS technology. (3) LC voltage controlled oscillator (VCO) performance degradation due to gate oxide breakdown effect is evaluated. (4) NBTI, HCI and BD combined effects on RF performance degradation are investigated. A physical picture illustrating the NBTI induced BD process is presented. A model to evaluate the time-to-failure (TTF) during NBTI is developed. DCIV method is used to extract the densities of NIT and NOT. Measurements show that there is direct correlation between the steplike increase in the gate current and the oxide-trapped charge (NOT). However, Breakdown has nothing to do with interface traps (NIT). (5) It is found that the degradation due to NSH stress is more severe than that of NS stress at high temperature. A model aiming to evaluate the stress-induced degradation is also developed.

This thesis work is mainly focused on studying RF performance degradation of a low noise amplifier (LNA) circuit due to hot carrier effect (HCE) in both the weak and strong inversion regions. Since the figures of merit for the RF circuit characterization are gain, noise figure, input, and output matching, the LNA RF performance drift is evaluated in a Cadence SpectreRF simulator subject to these features. This thesis presents hot carrier induced degradation results of an LNA to show that the HCE phenomenon is one of the serious reliability issues in the aggressively scaled RF CMOS design, especially for long-term operation of these devices. The predicted degradation from simulation results can be used design reliable CMOS RF circuits.

One of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices the peak of the lateral field is lowered by reducing the doping concentration near the drain and by providing a smooth junction transition instead of an abrupt one. Therefore, the amount of hot carrier generation for a given supply voltage and the influence of a certain physical damage on the electrical characteristics is decreased dramatically. A complete understanding of the hot carrier degradation problem in sub-micron 0.25um LD MOSFETs is presented in this work. First we discuss the degradation mechanisms observed under, for circuit operation, somewhat artificial but well-controlled uniform-substrate hot electron and substrate hot-hole injection conditions. Then the more realistic case of static channel hot carrier degradation is treated, and some important process-related effects are illustrated, followed by the behavior under the most relevant case for real operation, namely dynamic degradation. An Accurate and practical parameter extraction is used to obtain the LD MOSFETs model parameters, with the experiment verification. Good agreement between the model simulation and experiment is achieved. The gate charge transfer performance is examined to demonstrate the hot carrier effect. Furthermore, In order to understand the dynamic stress on the LD MOSFET and its effect on RF circuit, the hot-carrier injection experiment in which dynamic stress with different duty cycle applied to a LD MOS transistor is presented. A Class-C power amplifier is used to as an example to demonstrate the effect of dynamic stress on RF circuit performance. Finally, the strategy for improving hot carrier reliability and a forecast of the hot carrier reliability problem for nano-technologies are discussed. The main contribution of this work is, it systemically research the hot carrier reliability issue on the sub-micron lateral doped drain MOSFETs, which is induced by static and dynamic voltage stress; The stress condition mimics the typical application scenarios of LD MOSFET. Model parameters extraction technique is introduced with the aid of the current device modeling tools, the performance degradation model can be easily implement into the existing computer-aided tools. Therefore, circuit performance degradation can be accurately estimated in the design stage. CMOS technologies are constantly scaled down. The production on 65 nm is on the market. With the reduction in geometries, the devices become more vulnerable to hot carrier injection (HCI). HCI reliability is a must for designs implemented with new processes. Reliability simulation needs to be implemented in PDK libraries located on the modeling stage. The use of professional tools is a prerequisite to develop accurate device models, from DC to GHz, including noise modeling and nonlinear HF effects, within a reasonable time. Designers need to learn to design for reliability and they should be educated on additional reliability analyses. The value is the reduction of failure and redesign costs.

L'étude de la fiabilité représente un enjeu majeur de la qualification des technologies de l'industrie de la microélectronique. Elle est traditionnellement étudiée en suivant la dégradation des paramètres des transistors au cours du temps, qui sert ensuite à construire des modèles physiques expliquant le vieillissement des transistors. Nous avons fait le choix dans ces travaux d'étudier la fiabilité des transistors à l'échelle microscopique, en nous intéressant aux mécanismes de ruptures de liaisons atomiques à l'origine de la création des défauts de l'oxyde de grille. Nous avons tout d'abord identifié la nature des défauts et modéliser leurs dynamiques de capture de charges afin de pouvoir reproduire leur impact sur des mesures électriques complexes. Cela nous a permis de développer une nouvelle méthodologie de localisation des défauts, le long de l'interface Si-SiO2, ainsi que dans le volume de l'oxyde. La mesure des dynamiques de créations de défauts pour des stress de type porteurs chauds et menant au claquage de l'oxyde de grille nous a permis de développer des modèles de dégradation de l'oxyde, prédisant les profils de défauts créés à l'interface et dans le volume de l'oxyde. Nous avons enfin établi un lien précis entre l'impact de la dégradation d'un transistor sur la perte de fonctionnalité d'un circuit représentatif du fonctionnement d'un produit digital.L'étude et la modélisation de la fiabilité à l'échelle microscopique permet d'avoir des modèles plus physiques, offrant ainsi une plus grande confiance dans les extrapolations de durées de vie des transistors et des produits. / Reliability study is a milestone of microelectronic industry technology qualification. It is usually studied by following the degradation of transistors parameters with time, used to build physical models explaining transistors aging. We decided in this work to study transistors reliability at a microscopic scale, by focusing on atomic-bond-breaking mechanisms, responsible of defects creation into the gate-oxide. First, we identified defects nature and modeled their charge capture dynamics in order to reproduce their impact on complex electrical measurements degradation. This has allowed us developing a new methodology of defects localization, along the Si/SiO2 interface, and in the volume of the gate-oxide. Defects creation dynamics measurement, for Hot Carrier stress and stress conditions leading to the gate-oxide breakdown, has allowed us developing gate-oxide degradation models, predicting generated defect profiles at the interface and into the volume of the gate-oxide. Finally, we established an accurate link between a transistor degradation impact on circuit functionality loss.Reliability study and modeling at a microscopic scale allows having more physical models, granting a better confidence in transistors and products lifetime extrapolation.

The objective of the dissertation is to combine the recent Mixed-Mode reliability stress studies into a single text. The thesis starts with a review of silicon-germanium heterojunction bipolar transistor fundamentals, development trends, and the conventional reliability stress paths used in industry, after which the new stress path, Mixed-Mode stress, is introduced. Chapter 2 is devoted to an in-depth discussion of damage mechanisms that includes the impact ionization effct and the selfheating effect. Chapter 3 goes onto the impact ionization effect using two-dimensional calibrated MEDICI simulations. Chapter 4 assesses the reliability of SiGe HBTs in extreme temperature environments by way of comprehensive experiments and MEDICI simulations. A comparison of the device lifetimes for reverse-EB stress and mixed-mode stress indicates different damage mechanisms govern these phenomena. The thesis concludes with a summary of the project and suggestions for future research in chapter 5.

The higher mobility is needed for thin film transistor (TFT) mainly used to be applied in the larger size flat-panel displays (FPDs). The amorphous metal oxide TFT has mobility higher than 10 cm2/V¡Es and can substitute the poor mobility (<1 cm2/V¡Es) of traditional amorphous silicon TFT, which shows a great potential for the next generation. Due to the superior characteristics in amorphous metal oxide TFT, therefore, the amorphous metal oxide TFT has been studied extensively. Usually, the source/drain with island type device has a large overlapped/contact area that we cannot determine the exact electron path. That the sample of inverted stagger £\-IGZO TFTs with via type device has smaller contact area and can be estimated the electron path. In this thesis, the devices with different M1 overlaps etching stop layer (ESL) via distance, M2 £\-IGZO contact size and the fringe field effect are investigated. Although the characteristics of £\-IGZO TFTs have great performance, the electrical stability under illumination and long term bias stress are still a important issue to study before implement them into display. Thus, the devices with different structures that we mentioned previously are investigated the electrical reliability which are the negative bias stress of gate voltage, hot carrier stress effect and negative bias of illumination. The electron path of via type is extracted by contact resistance which is greater than the distance between S/D via. Experiment results show that the increased offset between M1 and ESL via generates the resistance-liked effect in electrical characteristics. The hot carrier stress effect is independent of M2 £\-IGZO contact size in short channel length devices and there are close depletion lengths in drain side. The negative bias stress of illumination is proceeded in the fringe field effect devices, which results a negative shift of threshold voltage due to the hole trapping.

La cellule photovoltaïque à porteurs chauds est un dispositif de conversion de l’énergie solaire en énergie électrique dont les rendements théoriques approchent les 86%. Additionnellement à une cellule photovoltaïque standard, ce dispositif permet de convertir l’excédent d’énergie cinétique des porteurs photogénérés, en énergie électrique. Pour cela, le phénomène de thermalisation doit être réduit et des contacts électriques sélectifs en énergie ajoutés. Afin de déterminer les performances potentielles des absorbeurs, tout en surmontant le défi de fabrication des contacts électriques sélectifs, un montage et une méthode de cartographie d’intensité absolue de photoluminescence résolue spectralement ont été utilisés. Ceci a permis d’obtenir la température d’émission et la séparation des quasi-niveaux de Fermi, les deux grandeurs thermodynamiques caractéristiques de la performance des absorbeurs. Dans cette étude, des absorbeurs à base de puits quantiques d’InGaAsP sur substrat d’InP sont utilisés. Les grandeurs thermodynamiques sont estimées et la technique de caractérisation utilisée permet l’accès à des grandeurs tel que le facteur de thermalisation mais aussi un coefficient thermoélectrique, appelé photo-Seebeck. L’analyse quantitative de porteurs chauds dans des conditions pertinentes pour le photovoltaïque est une première ; le dispositif étudié permettrait de dépasser la limite de Schockley-Queisser. Enfin, le dispositif étant muni de contacts des caractérisations électriques sont faites et comparé aux mesures optiques. Afin de mieux comprendre l’évolution des grandeurs thermodynamiques étudiées, une première simulation est proposée. / The hot carrier solar cell is an energy conversion device where theoretical conversion efficiencies reach almost 86%. Additionally to a standard photovoltaic cell, the device allows the conversion of kinetic energy excess of photogenerated carriers into electrical energy. To achieve this, the thermalisation process must be limited and electrical energy selective contacts added. In order to determine potential absorber performances and overcome the fabrication challenge of energy selective contacts, a set-up and the related method of mapping absolute photoluminescence spectra were used. This technique allows getting quasi-Fermi levels splitting and temperature of emission, both thermodynamic quantities characteristic of the performance of the absorbers. In this study, absorbers based on InGaAsP multiquantum wells on InP substrate were used. The thermodynamic quantities are determined and allow to access at quantities such as thermalisation rate but also a thermoelectric coefficient, so-called Photo-Seebeck. The quantitative analysis of the hot carriers regime, in relevant conditions for photovoltaic is a first: the analysed device indicates a potential photovoltaic conversion over the Schockley-Queisser limit. At last, as the device is supplied with electrical contacts, electrical characterization are made and compared to optical measurements. A first simulation is proposed to better understand the thermodynamic quantities evolution as a function of the electrical bias.

Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation

The rapid progress on developing new and improved multifunctional materials, for optoelectronic and spin based phenomena/devices, have increased the importance of the fundamental understanding of their coherent states and nonlinear optical properties. This study is aimed at characterizing, modeling, and controlling the fundamental electronic, phononic, and spin properties of several classes of materials through nonequilibrium and nonlinear light-matter interactions, coupled with a novel design of the material phases, interfaces, and heterostructures. This research directly addresses the Grand Challenges identified in the Basic Energy Sciences Advisory Committee report "Directing Matter and Energy: Five Challenges for Science and the Imagination" (Hemminger, 2007) [1], in particular, the area: "Matter far beyond equilibrium" and addresses the questions, "How do remarkable properties of matter emerge from complex correlations of the atomic or electronic constituents and how can we control these properties?" and "How do we design and perfect atom- and energy-efficient synthesis of revolutionary new forms of matter with tailored properties?". The knowledge gained from these fundamental studies can provide new information for a broad community to provide concepts for the next generation of multifunctional materials and devices, and resulted in several publications and conference presentations. The materials studied in this dissertation included multiferroic BaTiO3-BiFeO3 [2], ferroelectric Pb0.52Zr0.48TiO3 (PZT), InAs/AlAsSb multi-quantum-well [3], lead halide perovskite [4], n-type InAsP films [5, 6], and nanolaminate plasmonic crystals [7]. Probing multiferroics, which are materials that can exhibit ferromagnetic, ferroelectric, and ferroelastic orders simultaneously in a single phase, was a main focus of this study. BiFeO3 (BFO) is the most widely investigated multiferroic due to its high Neel and Curie temperatures and has antiferromagnetic and ferroelectric properties [8]. An inherent drawback of BFO is its large leakage currents. In this project, (1 − x)BaTiO3-(x)BiFeO3, x = 0.725 (BTO-BFO) heterostructures were investigated [9], where the conductivity of the solid solution can be reduced by adding another perovskite material, BaTiO3 [2]. We aimed to study optically induced coherent states in our BTO-BFO structures. Time resolved pumpprobe spectroscopic measurements were performed at room temperature as well as at low temperature (100 K) up to 10 T. Coherent acoustic phonons were observed both in a film and nanorods, resulting in coherent phonon frequencies of 27 and 33 GHz, respectively [2]. Coherent phonon spectroscopy is a sensitive tool to characterize the interfaces and can be employed as an effective ultrasensitive quantum sensor [10]. Furthermore, in the nanorods arrays of BTO-BFO, an additional oscillation with frequency in the range of 8.1 GHz was observed. This frequency is close to a theoretically predicted magnon frequency which could indicate the coexistence of coherent phonons and magnons in the nanorods arrays [2]. In an analogy to photonics which relies on electromagnetic waves, magnonics utilizes spin waves to carry and process information, offering several advantages such as an operation frequency in the THz range. Recently, "a quantum tango" [11] was reported where coupled coherent magnon and phonons modes were formed on a surface patterned ferromagnet. Furthermore, BTO-BFO heterostructures were probed using transient birefringence and magneto-optical Kerr effect spectroscopy. The results demonstrated that the magnetic field dependence of coherent phonons, measured by these two techniques, exhibits more sensitivity to the external magnetic fields compared to the differential reflectivity technique [2]. Moreover, nonlinear optical properties of this structure were investigated via second harmonic generation spectroscopy, where wavelength and polarization dependence of this nonlinear observation will be discussed in this dissertation. As part of this study, another class of multiferroic materials, with strong ferroelectric and piezoelectric properties, Pb0.52Zr0.48TiO3 (PZT) was studied [12]. In this project, the nonlinear optical properties of PZT nanorod arrays were investigated. Clear signatures of second harmonic generations from 490-525 nm (2.38-2.53 eV) at room temperature, were observed. Furthermore, time resolved differential reflectivity measurements were performed to study dynamical properties in the range of 690-1000 nm where multiphoton processes were responsible for the photoexcitations. We compared this excitation scheme, which is sensitive mainly to the surface states, to when the photoexcited energy (∼ 3.1 eV) was close to the bandgap of the nanorods. Our results offer promises for employing these nanostructures in nonlinear photonic applications. Furthermore, the established techniques during my research provided new insights on optical properties of InAs/AlAsSb multi-quantum-well [3], lead halide perovskite [4], n-type InAsP films [5, 6], and nanolaminate plasmonic crystals [7], and the results will be briefly presented in this dissertation. / Doctor of Philosophy / My research activities have explored multifunctional materials and heterostructures with strongly enhanced coupled electric and magnetic orders and optical properties. In particular, pursuing novel heterostructure designs such as multiferroics can provide control over electric and magnetic ordering in mixed dimensionality. This, together with control at the level from lattice structure to electron spin states can give rise to improved or even qualitatively new and robust materials properties. For example, a better understanding of the phenomena associated with the spin degree of freedom of electrons allows for advancement in spintronic device applications such as storage, logic, and sensors, which are associated with quantum computers and quantum communications [13, 14, 15]. Overarching questions and goals of my activities included: What are the microscopic origins and mechanisms of nonlinear response in strongly coupled nanostructured materials and its relationship to electronic, spin, and lattice degrees of freedom? (2) What are the effects of dimensionality and quantum confinement on optical properties? (3) How do we control and manipulate the coherent states, such as coherent phonons and magnons using external and internal fields, material composition, and morphology to achieve maximal efficiency and tunability? Addressing many of the challenges in the fast-paced technological world requires continued developments of new materials with enhanced optical properties. The knowledge gained from my fundamental studies can provide new information for the next generation of multifunctional materials and devices with advanced optical properties and resulted in several publications and conference presentations.

L’émission de lumière est une puissante technique de localisation dans le domaine de l’analyse de défaillance des circuits intégrés. Depuis plusieurs années, elle est utilisée comme une technique capable de localiser et d’identifier des défauts émissifs, tels que les courants de fuites, en fonctionnement statique du composant. Cependant, l’augmentation d’intégration et des performances des circuits actuels implique l’apparition d’émissions de défauts dynamiques dus à l’utilisation de fréquences de fonctionnement de plus en plus élevées. Ces contraintes imposent une adaptation de la technique d’émission de lumière qui doit donc évoluer en même temps que l’évolution des circuits intégrés. C’est dans ce contexte que de nouveaux modes de détection, liés à l’émission de lumière, est apparu : PICA et TRE. Ainsi, les photons sont collectés en fonction du temps donnant ainsi une place importante à la technique par émission de lumière dynamique pour le debbug et l’analyse de défaillance en procédant à une caractérisation précise des défauts issus des circuits intégrés actuels. Pour répondre aux exigences dues à l’analyse du comportement dynamique des circuits intégrés, des méthodes ont été identifiées à travers la technique PICA et la technique d’émission en temps résolu connue sous le nom de technique mono-point TRE. Cependant, les techniques PICA et TRE sont exposées à un défi continu lié à la diminution des technologies et donc des tensions d’alimentation. Pour analyser des circuits de technologies futures à faible tension d’alimentation, il est nécessaire de considérer différentes approches afin d’améliorer le rapport signal sur bruit. Deux solutions sont présentées dans ce document : un système de détection optimisé et des méthodes de traitement de signal. / Light emission is a powerful technique for the characterization of failed integrated circuits. For years, faults have been identified in a static configuration of the device. Just by providing the power supply, abnormal current leakage could be located. With the growing complexity of devices, some fault may appear only in the middle of the test sequence. As a result the evolution of light emission was to use the same detector to acquire the image of a running circuit. A new mode of light emission came became available: PICA or picoseconds IC analysis. With this configuration, photons are collected as a function of time. This technique became mainstream for IC debug and failure analysis to precisely characterize IC. Light emission has also reached dynamic IC requirements through PICA and Single-point PICA also known as TRE. However, light emission and TRE is facing a continuous challenge with technologies shrinkage and its associated power supply voltage drop. To work with recent IC technologies with ultra low VDD voltage, it is necessary to take a different approach, to improve the signal to ratio. Two solutions are presented in this document: A best detection system and TRE and PICA signal processing development.