The objective of this research is to develop an understanding of the trade-offs between performance and reliability in sub 100-nm silicon-on-insulator (SOI) CMOS technologies. Such trade-offs can be used to demonstrate high performance reliable circuits in scaled technologies. Several CMOS reliability concerns such as hot-carrier stress, ionizing irradiation damage, RF stress, temperature effects, and single-event effects are studied. These reliability mechanisms can cause temporary or permanent damage to the semiconductor device and to the circuits using them. Several improvements are made to the device layout and process to achieve optimum performance. Parasitics are shown to play a dominant role in the performance and reliability of sub 100-nm devices. Various techniques are suggested to reduce these parasitics, such as the use of the following: a) optimum device-width, b) optimum gate-finger to gate-finger spacing, c) optimum source/drain metal contact spacing, and d) floating-body/body-contact. The major contributions from this research are summarized as follows: 1) Role of floating-body effects on the performance and reliability of sub 100-nm CMOS-on-SOI technologies is investigated for the first time [1], [2]. It is demonstrated through experimental data and TCAD simulations that floating-body devices have improved RF performance but degraded reliability compared to body-contacted devices. 2) Floating-body effects in a cascode core is studied. Cascode cores are demonstrated to achieve much larger reliability lifetimes than a single device. A variety of cascode topologies are studied to achieve the trade-o s between performance and reliability for high-power applications [2]. 3) The use of body-contact to modulate the performance of devices and single-poledouble- throw (SPDT) switches is studied. The SPDT switch performance is shown to improve with a negative body-bias. 4) The impact of device width on the RF performance and reliability is studied. Larger width devices are shown to have greater degradation, posing challenging questions for RF design in strained-Si technologies [3]. 5) A novel study showing the e ect of source/drain metal contact spacing and gate-finger to gate-finger spacing on the device RF performance is carried out. Further, the impact of above on the hot-carrier, RF stress, and total-dose irradiation tolerance is studied [3], [4]. 6) Latchup phenomenon in CMOS is shown to be possible at cryogenic temperatures (below 50 K), and its consequences are discussed [5]. 7) A time-dependent device degradation model has been developed in technology computer aided design (TCAD) to model reliability in CMOS and SiGe devices. 8) The total-dose irradiation tolerance and hot-carrier reliability of 32-nm CMOSon- SOI technology is reported for the first time. The impact of HfO2 based gate dielectric on the performance and reliability is studied [6]. 9) The impact of technology scaling from 65-nm to 32-nm on the performance and reliability of CMOS technologies is studied [6]. 10) Cryogenic performance and reliability of 45-nm nFETs is investigated. The RF performance improves significantly at 77 K. The hot-carrier device reliability is shown to improve at low temperatures in short-channel CMOS technologies.

abstract: The aging process due to Bias Temperature Instability (both NBTI and PBTI) and Channel Hot Carrier (CHC) is a key limiting factor of circuit lifetime in CMOS design. Threshold voltage shift due to BTI is a strong function of stress voltage and temperature complicating stress and recovery prediction. This poses a unique challenge for long-term aging prediction for wide range of stress patterns. Traditional approaches usually resort to an average stress waveform to simplify the lifetime prediction. They are efficient, but fail to capture circuit operation, especially under dynamic voltage scaling (DVS) or in analog/mixed signal designs where the stress waveform is much more random. This work presents a suite of modelling solutions for BTI that enable aging simulation under all possible stress conditions. Key features of this work are compact models to predict BTI aging based on Reaction-Diffusion theory when the stress voltage is varying. The results to both reaction-diffusion (RD) and trapping-detrapping (TD) mechanisms are presented to cover underlying physics. Silicon validation of these models is performed at 28nm, 45nm and 65nm technology nodes, at both device and circuit levels. Efficient simulation leveraging the BTI models under DVS and random input waveform is applied to both digital and analog representative circuits such as ring oscillators and LNA. Both physical mechanisms are combined into a unified model which improves prediction accuracy at 45nm and 65nm nodes. Critical failure condition is also illustrated based on NBTI and PBTI at 28nm. A comprehensive picture for duty cycle shift is shown. DC stress under clock gating schemes results in monotonic shift in duty cycle which an AC stress causes duty cycle to converge close to 50% value. Proposed work provides a general and comprehensive solution to aging analysis under random stress patterns under BTI. Channel hot carrier (CHC) is another dominant degradation mechanism which affects analog and mixed signal circuits (AMS) as transistor operates continuously in saturation condition. New model is proposed to account for e-e scattering in advanced technology nodes due to high gate electric field. The model is validated with 28nm and 65nm thick oxide data for different stress voltages. It demonstrates shift in worst case CHC condition to Vgs=Vds from Vgs=0.5Vds. A novel iteration based aging simulation framework for AMS designs is proposed which eliminates limitation for conventional reliability tools. This approach helps us identify a unique positive feedback mechanism termed as Bias Runaway. Bias runaway, is rapid increase of the bias voltage in AMS circuits which occurs when the feedback between the bias current and the effect of channel hot carrier turns into positive. The degradation of CHC is a gradual process but under specific circumstances, the degradation rate can be dramatically accelerated. Such a catastrophic phenomenon is highly sensitive to the initial operation condition, as well as transistor gate length. Based on 65nm silicon data, our work investigates the critical condition that triggers bias runaway, and the impact of gate length tuning. We develop new compact models as well as the simulation methodology for circuit diagnosis, and propose design solutions and the trade-offs to avoid bias runaway, which is vitally important to reliable AMS designs. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2014

La cellule solaire à porteurs chauds est un dispositif à haut rendement de conversion qui permettrait de réduire significativement le coût de l’énergie qu’il génère. Ces cellules fonctionnent avec des électrons et des trous en non-équilibre thermique avec le réseau cristallin du materiau grâce à la réduction des pertes d’énergie des porteurs, nécessitant le développement de contacts électriques sélectifs en énergie des porteurs en non-équilibre. La conception des contacts sélectifs nécessite une bonne connaissance des propriétés des porteurs dans le matériau considéré. Une méthode permettant de séparer les propriétés de chaque porteur par l’analyse de spectres de photoluminescence du matériau est proposée. Disposant de mesures de photoluminescence résolues spatialement, une seconde méthode a été développée pour approcher les coefficients de transport de chaque porteur dans le matériau : ces coefficients sont mesurés en une seule fois, par une méthode optique sans contacts. Ensuite le fonctionnement des contacts sélectifs est détaillé, démontrant la difficulté d’une stabilité électrique du système en courant continu, contrairement aux dispositifs photovoltaïques classiques. Quelques pistes de fabrication expérimentales avec des molécules et des boîtes quantiques colloïdales ont également été étudiées. Enfin, en combinant les résultats de ces travaux sur le semiconducteur photosensible et sur les contacts, un modèle de simulation a été développé. Il intègre les principaux mécanismes de pertes des porteurs, résultant ainsi en une généralisation de différents modèles précédemment étudiés dans la littérature. Un lien entre le dispositif étudié et les machines thermiques est proposé. / The hot carrier solar cell is a high conversion yield device that could enable to significantly reduce thecost of the energy it generates. Unlike classical photovoltaic devices, these cells work with electronsand holes in thermal non-equilibrium with the lattice of the material, due to the reduction of thelosses by thermalization. This specific feature require the development of energy selective contacts fornon-equilibrium carriers. The design of energy selective contacts require a good knowledge of the carrier properties in the considered material. A method enabling to separate the properties of each carrier with the analysis of photoluminescence spectra of the material is proposed. Having spatially resolved photoluminescence measurements, a second method has been developed to estimate the transport coefficients of each carrier in the material: these coefficients are measured with a one-probe optical contactless technique. Then the working principle of the energy selective contacts is studied, showing thereby the challenge of a direct current electrical stability of the system, unlike classical photovoltaïc devices. Some experimental manufacturing with molecules and colloidal quantum dots have also been studied. Last, combining the obtained results on the semiconductor and on the contacts, a modeling tool breaking the symmetry between carriers has been developed. The model takes two principal loss mechanisms of the carrier into account, leading thereby to a generalization of different models previously studied in the literature. More global thermodynamic aspects also show the link between the studied device and the heat engines.

<p>We are in the midst of a technological revolution (popularly known as Industrie 4.0 or 4th Industrial Revolution) where our cars are being equipped with hundreds of sensors that make them safer, homes are becoming smarter, industry yields are at an all-time high, and internet-of-things is a reality. This was largely possible due to the developments in communication, electronics, motor controls, robotics, cyber security, software, efficient power distribution, etc. One of the major propellants of the 4th Industrial revolution is the ever-expanding applications of power electronics devices. All electrical energy will be provided, handled, and consumed through power electronics devices in the near future. Therefore, the reliability of power electronics devices will be instrumental in driving future technological advances. </p> <p> </p> <p><br></p><p>A myriad of devices is categorized as power electronics devices, and in the heart of those devices are the transistors. Although Silicon-based transistors still dominate the power electronics market, a paradigm shift towards wide bandgap semiconductors, such as silicon carbide (SiC), gallium nitride (GaN), beta-gallium oxide etc., is underway. However, realizing the full potential of these devices demands unconventional design, layout, and reliability. </p> <p> </p> <p>In this thesis, we try to establish a generalized model of reliability for power and logic transistors. We start by defining a comprehensive, substrate-, self-heating-, and reliability-aware safe operating area (SOA) that analytically establishes the optimum and self-consistent trade-off among breakdown voltage, power consumption, operating frequency, heat dissipation, and reliability before actual device fabrication. Then we take a deeper look into the reliability of individual transistors (a beta-gallium oxide transistor and a Silicon-based LDMOS), to test the predictions by the safe operating area, using both experiments and simulations. In the beta-gallium oxide transistor, we studied its implementation in a DC-DC voltage converter and concluded that the self-heating is a performance bottleneck and suggested approaches to alleviate it. For the LDMOS transistor, we investigated the hot carrier degradation (HCD) using experiments and simulations. We established that the HCD degradation kinetics is universal, and physics is the same as a classical transistor, despite a complicated geometry. Finally, we studied the correlation between HCD and radiation in LDMOS used in space shuttles, airplanes, etc., to determine its lifetime. </p><p><br></p> <p> </p> <p>We have holistically analyzed the reliability of power transistors by extending the theories of logic transistors in this thesis. Therefore, this thesis takes us a step closer to a generalized reliability model for power transistors by developing a comprehensive and predictive model for the safe operating area, encompassing all sources of stresses (e.g., electrical, thermal, and radiation) it experiences during operation.</p>

Modern technology needs and advancements have introduced various new concepts such as Internet-of-Things, electric automotive, and Artificial intelligence. This implies an increased activity in the electronics domain of analog and high frequency. Silicon devices have emerged as a cost-effective solution for such diverse applications. As these silicon devices are pushed towards higher performance, there is a continuous need to improve fabrication, power efficiency, variability, and reliability. Often, a direct trade-off of higher performance is observed in the reliability of semiconductor devices. The acceleration-based methodologies used for reliability assessment are the adequate time-saving solution for the lifetime's extrapolation but come with uncertainty in accuracy. Thus, the efforts to improve the accuracy of reliability characterization methodologies run in parallel. This study highlights two goals that can be achieved by incorporating high-frequency characterization into the reliability characteristics. The first one is assessing high-frequency performance throughout the device's lifetime to facilitate an accurate description of device/circuit functionality for high-frequency applications. Secondly, to explore the potential of high-frequency characterization as the means of scanning reliability effects within devices. S-parameters served as the high-frequency device's response and mapped onto a small-signal model to analyze different components of a fully depleted silicon-on-insulator MOSFET. The studied devices are subjected to two important DC stress patterns, i.e., Bias temperature instability stress and hot carrier stress. The hot carrier stress, which inherently suffers from the self-heating effect, resulted in the transistor's geometry-dependent magnitudes of hot carrier degradation. It is shown that the incorporation of the thermal resistance model is mandatory for the investigation of hot carrier degradation. The property of direct translation of small-signal parameter degradation to DC parameter degradation is used to develop a new S-parameter based bias temperature instability characterization methodology. The changes in gate-related small-signal capacitances after hot carrier stress reveals a distinct signature due to local change of flat-band voltage. The measured effects of gate-related small-signal capacitances post-stress are validated through transient physics-based simulations in Sentaurus TCAD.:Abstract Symbols Acronyms 1 Introduction 2 Fundamentals 2.1 MOSFETs Scaling Trends and Challenges 2.1.1 Silicon on Insulator Technology 2.1.2 FDSOI Technology 2.2 Reliability of Semiconductor Devices 2.3 RF Reliability 2.4 MOSFET Degradation Mechanisms 2.4.1 Hot Carrier Degradation 2.4.2 Bias Temperature Instability 2.5 Self-heating 3 RF Characterization of fully-depleted Silicon on Insulator devices 3.1 Scattering Parameters 3.2 S-parameters Measurement Flow 3.2.1 Calibration 3.2.2 De-embedding 3.3 Small-Signal Model 3.3.1 Model Parameters Extraction 3.3.2 Transistor Figures of Merit 3.4 Characterization Results 4 Self-heating assessment in Multi-finger Devices 4.1 Self-heating Characterization Methodology 4.1.1 Output Conductance Frequency dependence 4.1.2 Temperature dependence of Drain Current 4.2 Thermal Resistance Behavior 4.2.1 Thermal Resistance Scaling with number of fingers 4.2.2 Thermal Resistance Scaling with finger spacing 4.2.3 Thermal Resistance Scaling with GateWidth 4.2.4 Thermal Resistance Scaling with Gate length 4.3 Thermal Resistance Model 4.4 Design for Thermal Resistance Optimization 5 Bias Temperature Instability Investigation 5.1 Impact of Bias Temperature Instability stress on Device Metrics 5.1.1 Experimental Details 5.1.2 DC Parameters Drift 5.1.3 RF Small-Signal Parameters Drift 5.2 S-parameter based on-the-fly Bias Temperature Instability Characterization Method 5.2.1 Measurement Methodology 5.2.2 Results and Discussion 6 Investigation of Hot-carrier Degradation 6.1 Impact of Hot-carrier stress on Device performance 6.1.1 DC Metrics Degradation 6.1.2 Impact on small-signal Parameters 6.2 Implications of Self-heating on Hot-carrier Degradation in n-MOSFETs 6.2.1 Inclusion of Thermal resistance in Hot-carrier Degradation modeling 6.2.2 Convolution of Bias Temperature Instability component in Hot-carrier Degradation 6.2.3 Effect of Source and Drain Placement in Multi-finger Layout 6.3 Vth turn-around effect in p-MOSFET 7 Deconvolution of Hot-carrier Degradation and Bias Temperature Instability using Scattering parameters 7.1 Small-Signal Parameter Signatures for Hot-carrier Degradation and Bias Temperature Instability 7.2 TCAD Dynamic Simulation of Defects 7.2.1 Fixed Charges 7.2.2 Interface Traps near Gate 7.2.3 Interface Traps near Spacer Region 7.2.4 Combination of Traps 7.2.5 Drain Series Resistance effect 7.2.6 DVth Correction 7.3 Empirical Modeling based deconvolution of Hot-carrier Degradation 8 Conclusion and Recommendations 8.1 General Conclusions 8.2 Recommendations for Future Work A Directly measured S-parameters and extracted Y-parameters B Device Dimensions for Thermal Resistance Modeling C Frequency response of hot-carrier degradation (HCD) D Localization Effect of Interface Traps Bibliography

Solar energy is one of the most promising sources of confronting the energy crisis. And hot carrier solar cell can be the future to increase the efficiency of solar cells to exceed to the theoretical efficiency limit, Shockley-Queisser limit. After theoretical understanding of some essential aspects of hot carrier solar cell, to better understand the properties of hot carriers and the thermalization mechanisms behind it, analysis is conducted based on the photoluminescence spectra of GaAs thin-film absorber samples with different thicknesses. According to the results of the analysis, information on the properties of hot carriers in thin-film GaAs absorbers will be extracted, as well as a conclusion based on those results. / Solenergi är en av de mest lovande källorna för att konfrontera energikrisen. Och heta bärsolceller kan vara framtiden för att öka solcellernas effektivitet till att överskrida den teoretiska effektivitetsgränsen, Shockley-Queisser-gränsen. Efter teoretisk förståelse av några väsentliga aspekter av varmbärarsolceller, för att bättre förstå egenskaperna hos heta bärare och termismeringsmekanismerna bakom den, utförs analys baserad på fotoluminescensspektra för GaAs tunnfilmsabsorberprover med olika tjocklekar. Enligt resultaten av analysen kommer information om egenskaperna hos heta bärare i tunnfilmiga GaA-absorberare att extraheras, liksom en slutsats baserad på dessa resultat.

L’avantage de cette architecture FDSOI par rapport à l’architecture Si-bulk est qu’elle possède une face arrière qui peut être utilisée comme une deuxième grille permettant de moduler la tension de seuil Vth du transistor. Pour améliorer les performances des transistors canal p (PMOS), du Germanium est introduit dans le canal (SiGe) et au niveau des sources/drain pour la technologie 14nm FDSOI. Par ailleurs, la réduction de la géométrie des transistors à ces dimensions nanométriques fait apparaître des effets de design physique qui impactent à la fois les performances et la fiabilité des transistors.Ce travail de recherche est développé sur quatre chapitres dont le sujet principal porte sur les performances et la fiabilité des dernières générations CMOS soumises aux mécanismes de dégradation BTI (Bias Temperature Instability) et par injections de porteurs chauds (HCI) dans les dernières technologies 28nm et 14nm FDSOI. Dans le chapitre I, nous nous intéressons à l’évolution de l’architecture du transistor qui a permis le passage des nœuds Low-Power 130-40nm sur substrat silicium à la technologie FDSOI (28nm et 14nm). Dans le chapitre II, les mécanismes de dégradation BTI et HCI des technologies 28nm et 14nm FDSOI sont étudiés et comparés avec les modèles standards utilisés. L’impact des effets de design physique (Layout) sur les paramètres électriques et la fiabilité du transistor sont traités dans le chapitre III en modélisant les contraintes induites par l’introduction du SiGe. Enfin le vieillissement et la dégradation des performances en fréquence ont été étudiés dans des circuits élémentaires de type oscillateurs en anneau (ROs), ce qui fait l’objet du chapitre IV. / The subject of this thesis developed on four chapters, aims the development of advanced CMOS technology nodes fabricated by STMicroelectronics in terms of speed performance and reliability. The main reliability issues as Bias Temperature Instability (BTI) and Hot-Carriers (HC) degradation mechanisms have been studied in the most recent 28nm and 14nm FDSOI technologies nodes. In the first chapter, we presents the evolution of transistor architecture from the low-power 130-40nm CMOS nodes on silicon substrate to the recent FDSOI technology for 28nm and 14nm CMOS nodes. The second chapter presents the specificity of BTI and HCI degradation mechanisms involved in 28nm and 14nm FDSOI technology nodes. In the third chapter, we have studied the impact of layout effects on device performance and reliability comparing symmetrical and asymmetrical geometries. Finally the trade-off between performance and reliability is studied in the fourth chapter using elementary circuits. The benefit of using double gate configuration with the use of back bias VB in FDSOI devices to digital cells, allows to compensate partially or totally the aging in ring oscillators (ROs) observed by the frequency reduction. This new compensation technique allows to extend device and circuit lifetime offering a new way to guaranty high frequency performance and long-term reliability.

Frontend and backend wearout mechanisms are major reliability concerns for modern microprocessors. In this research, a framework which contains modules for negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate-oxide breakdown (GOBD), backend time-dependent dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV) is proposed to analyze the impact of each wearout mechanism on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Taking into account the detailed thermal profiles, electrical stress profiles and a variety of use scenarios, composed of a fraction of time in operation, a fraction of time in standby, and a fraction of time when the system is off, this work provides insight into lifetime-limiting wearout mechanisms, along with the reliability-critical microprocessor functional units for a system. This enables circuit designers to know if their designs will achieve an adequate lifetime and further make any updates in the designs to enhance reliability prior to committing the designs to manufacture.

Avec la tendance continue vers la technologie nanométrique et l'augmentation des fonctions complexes intègres dans les électroniques systèmes embarqués, Assurant la compatibilité électromagnétique (CEM) des systèmes électroniques est un grand défi. CEM est devenu une cause majeure de redesign des Circuits intègres (CI). D’ailleurs, les performances des circuits pourraient être affectés par les mécanismes de dégradation tels que hot carrier injection (HCI), negative bias temperature instability (NBTI), gate oxide breakdown, qui sont accélérés par les conditions d'exploitation extrême (haute / basse température, surcharge électrique, le rayonnement). Ce vieillissement naturel peut donc affecter les performances CEM des circuits intégrés.Les travaux développés dans notre laboratoire vise à clarifier le lien entre les dégradations induites par le vieillissement et les dérives CEM, de développer les modèles de prédiction et de proposer des "insensibles au cours du temps" structures pour CEM protection, afin de fournir des méthodes et des guidelines aux concepteurs d'équipements et CI pour garantir la CEM au cours de durée de vie de leurs applications. Ce sujet de recherche est encore sous-exploré en tant que communautés de recherche sur la «fiabilité IC» et «compatibilité électromagnétique IC» n’a souvent pas de chevauchement.Ce manuscrit de thèse introduit une méthode pour quantifier l'effet du vieillissement sur les CEM des circuits intégrés par la mesure et la simulation. Le premier chapitre donne un aperçu du contexte général et le deuxième chapitre est dédié a l’état de l'art de CEM des circuits intégrés et de problèmes de fiabilité IC. Les résultats expérimentaux de circuits CEM évolution sont présentés dans le troisième chapitre. Ensuite, le quatrième chapitre est consacré à la caractérisation et la modélisation des mécanismes de dégradation du CI. Un EMR modèle qui inclut l'élément le vieillissement pour prédire la dérive du niveau CEM de notre puce de test après stress est proposé / With the continuous trend towards nanoscale technology and increased integration of complex electronic functions in embedded systems, ensuring the electromagnetic compatibility (EMC) of electronic systems is a great challenge. EMC has become a major cause of IC redesign. Meanwhile, ICs performance could be affected by the degradation mechanisms such as hot carrier injection (HCI), negative bias temperature instability(NBTI), gate oxide breakdown, which are accelerated by the harsh operation conditions (high/low temperature, electrical overstress, radiation). This natural aging can thus affect EMC performances of ICs. The work developed in our laboratory aims at clarifying the link between ageing induced IC degradations and related EMC drifts, developing prediction models and proposing “time insensitive” EMC protection structures, in order to provide methods and guidelines to IC and equipment designers to ensure EMC during lifetime of their applications. This research topic is still under-explored as research communities on “IC reliability” and “IC electromagnetic compatibility” has often no overlap. The PhD manuscript introduced a methodology to quantify the effect of ageing on EMC of ICs by measurement and simulation. The first chapter gives an overview of the general context and the second chapter states the EMC of ICs state of the art and IC reliability issues. The experimental results of ICs EMC evolution are presented in the third chapter. Then, the fourth chapter is dedicated to the characterization and modeling IC degradation mechanism. An EMR model which includes the ageing element to predict our test chip’s EMC level drift after stress is proposed

Actuellement, les circuits numériques nécessitent d'être de plus en plus performants. Aussi, les produits doivent être conçus le plus rapidement possible afin de gagner les précieuses parts de marché. Les méthodes rapides de conception et l'utilisation de MPSoC ont permis de satisfaire à ces exigences, mais sans tenir compte précisément de l'impact du vieillissement des circuits sur la conception. Or les MPSoC utilisent les technologies de fabrication les plus récentes et sont de plus en plus soumis aux défaillances matérielles. De nos jours, les principaux mécanismes de défaillance observés dans les transistors des MPSoC sont le HCI et le NBTI. Des marges sont alors ajoutées pour que le circuit soit fonctionnel pendant son utilisation, en considérant le cas le plus défavorable pour chaque mécanisme. Ces marges deviennent de plus en plus importantes et diminuent les performances attendues. C'est pourquoi les futures méthodes de conception nécessitent de tenir compte des dégradations matérielles en fonction de l’utilisation du circuit. Dans cette thèse, nous proposons une méthode originale pour simuler le vieillissement des MPSoC à haut niveau d'abstraction. Cette méthode s'applique lors de la conception du système c.-à-d. entre l'étape de définition des spécifications et la mise en production. Un modèle empirique permet d'estimer les dégradations temporelles en fin de vie d'un circuit. Un exemple d'application est donné pour un processeur embarqué et les résultats pour un ensemble d'applications sont reportés. La solution proposée permet d'explorer différentes configurations d'une architecture MPSoC pour comparer le vieillissement. Aussi, l'application la plus sévère pour le vieillissement peut être identifiée. / Nowadays, more and more performance is expected from digital circuits. What’s more, the market requires fast conception methods, in order to propose the newest technology available. Fast conception methods and the utilization of MPSoC have enabled high performance and short time-to-market while taking little attention to aging. However, MPSoC are more and more prone to hardware failures that occur in transistors. Today, the prevailing failure mechanisms in MPSoC are HCI and NBTI. Margins are usually added on new products to avoid failures during execution, by considering worst case scenario for each mechanism. For the newest technology, margins are becoming more and more important and products performance is getting lower and lower. That’s why the conception needs to take into account hardware failures according to the execution of software. This thesis propose a new methodology to simulate aging at high level of abstraction, which can be applied to MPSoC. The method can be applied during product conception, between the specification phase and the production. An empirical model is used to estimate slack time at circuit's end of life. A use case is conducted on an embedded processor and degradation results are reported for a set of applications. The solution enables architecture exploration and MPSoC aging can thus be compared. The software with most severe impact on aging can also be determined.