<p>Communication and digital signal processing applications of today are often developed as fully integrated systems on one single chip and are implemented as application specific integrated circuits using e.g. VLSI technology. As the systems are getting more and more complex in terms of speed and performance the chip size and the design time tend to increase rapidly. This will result in search for cheaper and less time consuming alternatives. One alternative is field programmable gate arrays, so called FPGAs. The FPGAs are getting faster, cheaper and the number of gates increases all the time. A long list of ready to use functional blocks so called intellectual property (IP) blocks can be used in FPGAs. The latest FPGAs can also be bought with one or more embedded processors, in form of hard processor cores or as licenses for soft processor cores. This will speed up the design phase and of course also decrease the crucial time to market even more. </p><p>The purpose of this master’s thesis was to develop a waveform generator to generate a sine signal and a cosine signal, I and Q, used for radio/radar applications. The digital signals should have an output data rate of at least 100 MHz. The digital part of the system should be implemented in hardware using e.g. an FPGA. To convert the digital signals to analog signals two D/A converters are used. The analog signals, I and Q, should have a bandwidth of 1 MHz - 11 MHz. </p><p>The waveform generator was developed and implemented using a Virtex II FPGA from Xilinx. An embedded microprocessor within the FPGA, MicroBlaze, in form of a soft processor core was used to control the system. A user interface program running on the microprocessor was also developed. Testing of the whole system, both hardware and software, was done. The system is able to generate digital sine and cosine curves of an output data rate of 100 MHz.</p>

Communication and digital signal processing applications of today are often developed as fully integrated systems on one single chip and are implemented as application specific integrated circuits using e.g. VLSI technology. As the systems are getting more and more complex in terms of speed and performance the chip size and the design time tend to increase rapidly. This will result in search for cheaper and less time consuming alternatives. One alternative is field programmable gate arrays, so called FPGAs. The FPGAs are getting faster, cheaper and the number of gates increases all the time. A long list of ready to use functional blocks so called intellectual property (IP) blocks can be used in FPGAs. The latest FPGAs can also be bought with one or more embedded processors, in form of hard processor cores or as licenses for soft processor cores. This will speed up the design phase and of course also decrease the crucial time to market even more. The purpose of this master’s thesis was to develop a waveform generator to generate a sine signal and a cosine signal, I and Q, used for radio/radar applications. The digital signals should have an output data rate of at least 100 MHz. The digital part of the system should be implemented in hardware using e.g. an FPGA. To convert the digital signals to analog signals two D/A converters are used. The analog signals, I and Q, should have a bandwidth of 1 MHz - 11 MHz. The waveform generator was developed and implemented using a Virtex II FPGA from Xilinx. An embedded microprocessor within the FPGA, MicroBlaze, in form of a soft processor core was used to control the system. A user interface program running on the microprocessor was also developed. Testing of the whole system, both hardware and software, was done. The system is able to generate digital sine and cosine curves of an output data rate of 100 MHz.

This thesis includes two topics. One is a low-power high-speed 8-bit pipelining CLA design using dual threshold voltage (dual- Vth) domino logic. The other is a low-cost digital I/Q separator for DVB-T receivers. A high speed and low power 8-bit CLA using dual- Vth domino logic blocks arranged in a PLA-like style with pipelining is presented. According to parallely precharge and sequentially evaluate in a cascaded set of domino logic blocks, transistors in the precharge part and the evaluation part of dual- Vth domino logic are, respectively, replaced by high Vth transistors to reduce subthreshold leakage current through OFF transistors, and low Vth transistors. Moreover, an nMOS transistor is inserted in the precharge phase of the output inverter such that the two-phase dual- Vth domino logic can be properly applied in a pipeline structure. Consequently, the proposed design keeps the advantage of high speed while attaining the effect of low power dissipation. A low-cost digital I/Q separator is presented in the second part of this thesis. Using digital I/Q separator in place of the traditional analog I/Q separator guarantees the design conquer gain and phase mismatch problems between the I and Q channels. The proposed design can berealized by inverters and shifters such that the goal of low cost can be achieved.

abstract: Built-in-Self-Test (BiST) for transmitters is a desirable choice since it eliminates the reliance on expensive instrumentation to do RF signal analysis. Existing on-chip resources, such as power or envelope detectors, or small additional circuitry can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as IQ imbalance, is challenging. In this work, a BiST technique to compute transmitter IQ imbalances using measurements out of a self-mixing envelope detector is proposed. Both the linear and non linear parameters of the RF transmitter path are extracted successfully. We first derive an analytical expression for the output signal. Using this expression, we devise test signals to isolate the effects of gain and phase imbalance, DC offsets, time skews and system nonlinearity from other parameters of the system. Once isolated, these parameters are calculated easily with a few mathematical operations. Simulations and hardware measurements show that the technique can provide accurate characterization of IQ imbalances. One of the glaring advantages of this method is that, the impairments are extracted from analyzing the response at baseband frequency and thereby eliminating the need of high frequency ATE (Automated Test Equipment). / Dissertation/Thesis / M.S. Electrical Engineering 2012

This study is an attempt to ascertain if there is a relationship between academic achievement, I. Q. and social maturity in mentally retarded children in an institutional setting.

This thesis consists of two research projects on wireless communication systems. In the first project, we propose a fast inphase and quadrature (I/Q) imbalance compensation technique for the analog quadrature modulators in direct conversion transmitters. The method needs no training sequence, no extra background data gathering process and no prior perfect knowledge of the envelope detector characteristics. In contrast to previous approaches, it uses points from both the linear and predictable nonlinear regions of the envelope detector to hasten convergence. We provide a least mean square (LMS) version and demonstrate that the quadrature modulator compensator converges. In the second project, we propose a technique to deceive the automatic gain control (AGC) block in an eavesdropper's receiver to increase wireless physical layer data transmission secrecy. By sharing a key with the legitimate receiver and fluctuating the transmitted signal power level in the transmitter side, a positive average secrecy capacity can be achieved even when an eavesdropper has the same or even better additive white gaussian noise (AWGN) channel condition. Then, the possible options that an eavesdropper may choose to fight against our technique are discussed and analyzed, and approaches to eliminate these options are proposed. We demonstrate that a positive average secrecy capacity can still be achieved when an eavesdropper uses these options.

Tato práce se zaměřuje na klasifikaci vysokofrekvenčních vysílačů v závislosti na nedokonalostech jejich komponent pomocí algoritmu strojového učení. Práce je rozdělena na dvě části - teoretickou a praktickou.V teoretické části je nejprve popsána základní struktura vysílače s přímou konverzí a jsou uvedeny nedokonalosti rádiového front-endu, které mohou být využity ke klasifikaci. Dále jsou vysvětleny vybrané metody strojového učení s učitelem, zejména metoda support vector machines a neuronové sítě. Praktická část se zabývá implementací a dosaženými výsledky těchto dvou metod v prostředí MATLAB na problému klasifikace rádiových front-endů.

Thesis (PhD (Electrical and Electronic Engineering))--University of Stellenbosch, 2011. / ENGLISH ABSTRACT: The use of the quadrature mixing topology has been severely limited in the past due to its sensitivity towards mismatches between its signal paths. In recent years, researchers have suggested that digital techniques can be used to compensate for the impairments in the analogue quadrature mixing front-end. Most authors, however, focus on the modelling and compensation of frequency-independent imbalances, reasoning that this approach is sufficient for narrow band signal operation. This common assumption is, however, becoming increasing less applicable as the use of wider bandwidth signals and multi-channel systems becomes more prevalent. In this dissertation, baseband equivalent distortion models are derived, which model frequency-independent, as well as frequency-dependent contributions towards the imbalances of the front-end. Both lowpass and bandpass imbalances are modelled, which extends current modelling approaches found in literature. The resulting baseband models are shown to be capable of explaining the imbalance characteristics observed in practical quadrature mixing front ends, where existing models fail to do so. The developed imbalance models is then used to develop novel frequency-dependent imbalance extraction and compensation techniques, which directly extract the exact quadrature imbalances of the front end, using simple test tones. The imbalance extraction and compensation procedures are implemented in the digital baseband domain of the transceiver and do not require high computational complexity. The performance of these techniques are subsequently verified through simulations and a practical hardware implementation, yielding significant improvement in the image rejection capabilities of the quadrature mixing transceiver. Finally, a novel, blind imbalance compensation technique is developed. This technique is aimed at extracting frequency-independent I/Q imbalances in systems employing digital modulation schemes. No test tones are employed and the imbalances of the modulator and demodulator are extracted from the second order statistics of the received signal. Simulations are presented to investigate the performance of these techniques under various operating conditions. / AFRIKAANSE OPSOMMING: Die gebruik van die haaksfasige mengtopologie word geweldig beperk deur die sensitiwiteit vir wanbalanse wat mag bestaan tussen die twee analoog seinpaaie. In die afgelope paar jaar het navorsers digitale metodes begin voorstel om te kompenseer vir hierdie wanbalanse in die analooggebied. Meeste navorsers fokus egter op frekwensie-onafhanklike wanbalanse. Hulle staaf hierdie aanslag deur te redineer dat dit ’n aanvaarbare aaname is vir ’n nouband stelsel. Hierdie algemene aanvaarding is egter besig om minder akkuraat te raak, namate wyeband- en multikanaalstelses aan die orde van die dag raak. In hierdie tesis word basisband-ekwiwalente wanbelansmodelle afgelei wat poog om die effek van frekwensie-afhanklike en -onafhanklike wanbalanse akkuraat voor te stel. Beide laagdeurlaat- en banddeurlaatwanbalanse word gemodelleer, wat ‘n uitbreiding is op die huididge modellerings benaderings wat in literatuur gevind word. Dit word aangetoon dat die modelle van hierdie tesis daarin slaag om die karakteristieke van ’n werklike haaksfasige mengstelsel akkuraat te vervat – iets waarin huidige modelle in die literatuur nie slaag nie. Die basisband-ekwiwalente modelle word dan gebruik om nuwe digitale kompensasie metodes te ontwikkel, wat daarin slaag om die frekwensie-afhanklike wanbalanse van die haaksfasige mengstelsel af te skat, en daarvoor te kompenseer in die digitale deel van die stelsel. Hierdie kompensasiemetodes gebruik eenvoudige toetsseine om die wanbalanse af te skat. Die werksverrigting van hiedie kompensasiemetodes word dan ondersoek deur middel van simulasies en ’n praktiese hardeware-implementasie. Die resultate wys daarop dat hierdie metodes daarin slaag om ’n aansienlike verbetering in die beeldonderdrukkingsvermo¨ens van die haaksfasige mengers te weeg te bring. Laastens word daar ook ’n blinde kompensasiemetode ontwikkel, wat gemik is op frekwensie- onafhanklike wanbalanse in digital-modulasie-skama stelsels. Vir hierdie metodes is geen toetsseine nodig om die wanbalanse af te skat nie, en word dit gedoen vanuit die tweede-orde statistiek van die ontvangde sein. Die werksverrigting van hierdie tegnieke word verder bevestig deur middel van simulasies.

The Decimator, an SED Systems Ltd. product, is a PCI slot card that performs both time and frequency domain measurements of given input signals. It is essentially a more economical version of a bench spectrum analyzer or oscilloscope, with a PC interface. Several issues limit the speed and accuracy of the results of the Decimator, and the study of these issues is the focus of this thesis. These issues, including but not limited to, are as follows: 1) Imbalances between the received In-phase and Quadrature-phase channels; 2) The FFT and Windowing functions are performed by a microcontroller, but it is desired that they be migrated to an FPGA. While solutions to improve the first issue is being implemented and verified, the second issue is not one of simply reducing a source of error. The second issue requires a cost-benefit analysis on the migration of these signal processing algorithms from an ARM microcontroller to a Xilinx FPGA.

The Decimator, an SED Systems Ltd. product, is a PCI slot card that performs both time and frequency domain measurements of given input signals. It is essentially a more economical version of a bench spectrum analyzer or oscilloscope, with a PC interface. Several issues limit the speed and accuracy of the results of the Decimator, and the study of these issues is the focus of this thesis. These issues, including but not limited to, are as follows: 1) Imbalances between the received In-phase and Quadrature-phase channels; 2) The FFT and Windowing functions are performed by a microcontroller, but it is desired that they be migrated to an FPGA. While solutions to improve the first issue is being implemented and verified, the second issue is not one of simply reducing a source of error. The second issue requires a cost-benefit analysis on the migration of these signal processing algorithms from an ARM microcontroller to a Xilinx FPGA.