Thesis (Ph.D.)--University of Delaware, 2006. / Principal faculty advisor: Michael W. Haney, Dept. of Electrical and Computer Engineering. Includes bibliographical references.

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Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by James D. Miendl. / Vita. Includes bibliographical references.

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Stress induced void formation in Cu interconnects, due to thermal stresses generated during the processing of semiconductors, is an increasing reliability issue in the semiconductor industry as Cu interconnects are being downscaled to follow the demand for faster chip speed. In this work, 1.8 micron and 180 nm wide Cu interconnects, fabricated by Freescale Semiconductors, were subjected to thermal cycles, in-situ in the TEM, to investigate the stress relaxation mechanisms as a function of interconnect linewidth. The experiments show that the 1.8 micron Cu interconnect lines relax the thermal stresses through dislocation nucleation and motion while the Cu interconnect 180 nm lines exhibit void formation. Void formation in 180 nm lines occurs predominantly at triple junctions where the Ta diffusion barrier meets a Cu grain boundary. In order to understand void formation in 180 nm lines, the grain orientation and local stresses are determined. In particular, Nanobeam Diffraction (NBD) in the TEM is used to obtain the diffraction pattern of each grain, from which the crystal orientation is evaluated by the ACT (Automated Crystallography for TEM) software. In addition, 2D Finite Element Method (FEM) simulations are performed using the Object Oriented Finite Modeling (OOF2) software to correlate grain orientation with local stresses, and consequently void formation. According to the experimental and simulation results obtained, void formation in 180nm Cu interconnects does not seem to be solely dependent on local stresses, but a combination of diffusion paths available, stress gradients and possibly the presence of defects. In addition, based on the in-situ TEM observations, void growth seems to occur through grain boundary and/or interfacial diffusion. However, in-situ STEM observations of fully opened voids post-failure show pileup of material at the Cu grain surfaces. This means that surface or interface diffusion is also very active during void growth in the presence of thermal stresses.

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