Thesis (Ph. D.)--Washington State University, August 2007. / Includes bibliographical references (p. 89-97).

In search of higher speed and integration, the integrated circuit (IC) technology is scaling down. The total on-chip interconnect length is increasing exponentially. In fact, interconnect takes up the most part of the total chip area. The parasitics associated with these interconnect have significant impact on the circuit performance. Some of the effects of parasitics include cross talk, voltage drop and high current density. These issues can result in cross-talk induced functional failure and failures due to IR drop and electro-migration. This has resulted in interconnect- driven design trend in state-of-the-art integrated circuits. Reliability analysis, that includes simulating the effects of parasitics for voltage drop, current density, has become one of the most important steps in the VLSI design flow. Most of the CAD/EDA tools available, map these analysis results two dimensionally. Al- though this helps the designer, providing a three dimensional view of these results is highly desirable when dealing with complex circuits. In pursuit of visualizing reliability analysis results three dimensionally, as a first step, this work presents a tool that can visualize IC interconnect three di- mensionally. Throughout the course of this research open source tools were used to achieve the objective. In this work the circuit layout is stored as an OpenAc- cess database. A C++ program reads the design information using OpenAccess API and converts it to the .OBJ file format. Art of Illusion, an open source 3D modeling and rendering tool, reads this .OBJ file and models the IC interconnect three-dimensionally. In addition, Eclipse, an open source java IDE is used as a development platform. The tool presented has the capability to zoom in, zoom out and pan in real time.

No description available.

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy

Sham Chiu Wing. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 107-113). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.1 / Chapter 1.2 --- Progress on the Problem --- p.2 / Chapter 1.3 --- Our Contributions --- p.3 / Chapter 1.4 --- Thesis Organization --- p.5 / Chapter 2 --- Preliminaries --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.1.1 --- The Role of Floorplanning --- p.6 / Chapter 2.1.2 --- Wirelength Estimation --- p.7 / Chapter 2.1.3 --- Different Types of Floorplan --- p.8 / Chapter 2.2 --- Representations of Floorplan --- p.10 / Chapter 2.2.1 --- Polish Expressions --- p.10 / Chapter 2.2.2 --- Sequence Pair --- p.11 / Chapter 2.2.3 --- Bounded-Sliceline Grid (BSG) Structure --- p.13 / Chapter 2.2.4 --- O-Tree --- p.14 / Chapter 2.2.5 --- B*-Tree --- p.16 / Chapter 2.2.6 --- Corner Block List --- p.18 / Chapter 2.2.7 --- Twin Binary Tree --- p.19 / Chapter 2.2.8 --- Comparisons between Different Representations --- p.20 / Chapter 2.3 --- Algorithms of Floorplan Design --- p.20 / Chapter 2.3.1 --- Constraint Based Floorplanning --- p.21 / Chapter 2.3.2 --- Integer Programming Based Floorplanning --- p.21 / Chapter 2.3.3 --- Neural Learning Based Floorplanning --- p.22 / Chapter 2.3.4 --- Rectangular Dualization --- p.22 / Chapter 2.3.5 --- Simulated Annealing --- p.23 / Chapter 2.3.6 --- Genetic Algorithm --- p.23 / Chapter 2.4 --- Summary --- p.24 / Chapter 3 --- Literature Review on Interconnect-Driven Floorplanning --- p.25 / Chapter 3.1 --- Introduction --- p.25 / Chapter 3.2 --- Simulated Annealing Approach --- p.25 / Chapter 3.2.1 --- """Pepper - A Timing Driven Early Floorplanner""" --- p.25 / Chapter 3.2.2 --- """A Timing Driven Block Placer Based on Sequence Pair Model""" --- p.26 / Chapter 3.2.3 --- """Integrated Floorplanning and Interconnect Planning""" --- p.27 / Chapter 3.2.4 --- """Interconnect Driven Floorplanning with Fast Global Wiring Planning and Optimization""" --- p.27 / Chapter 3.3 --- Genetic Algorithm Approach --- p.28 / Chapter 3.3.1 --- "“Timing Influenced General-cell Genetic Floorplanning""" --- p.28 / Chapter 3.4 --- Force Directed Approach --- p.29 / Chapter 3.4.1 --- """Timing Influenced Force Directed Floorplanning""" --- p.29 / Chapter 3.5 --- Congestion Planning --- p.30 / Chapter 3.5.1 --- """On the Behavior of Congestion Minimization During Placement""" --- p.30 / Chapter 3.5.2 --- """Congestion Minimization During Placement""" --- p.31 / Chapter 3.5.3 --- "“Estimating Routing Congestion Using Probabilistic Anal- ysis""" --- p.31 / Chapter 3.6 --- Buffer Planning --- p.32 / Chapter 3.6.1 --- """Buffer Block Planning for Interconnect Driven Floor- planning""" --- p.32 / Chapter 3.6.2 --- """Routability Driven Repeater Block Planning for Interconnect- centric Floorplanning""" --- p.33 / Chapter 3.6.3 --- """Provably Good Global Buffering Using an Available Block Plan""" --- p.34 / Chapter 3.6.4 --- "“Planning Buffer Locations by Network Flows""" --- p.34 / Chapter 3.6.5 --- """A Practical Methodology for Early Buffer and Wire Re- source Allocation""" --- p.35 / Chapter 3.7 --- Summary --- p.36 / Chapter 4 --- Floorplanner with Fixed Buffer Planning [34] --- p.37 / Chapter 4.1 --- Introduction --- p.37 / Chapter 4.2 --- Overview of the Floorplanner --- p.38 / Chapter 4.3 --- Congestion Model --- p.38 / Chapter 4.3.1 --- Construction of Grid Structure --- p.39 / Chapter 4.3.2 --- Counting the Number of Routes at a Grid --- p.40 / Chapter 4.3.3 --- Buffer Location Computation --- p.41 / Chapter 4.3.4 --- Counting Routes with Blocked Grids --- p.42 / Chapter 4.3.5 --- Computing the Probability of Net Crossing --- p.43 / Chapter 4.4 --- Time Complexity --- p.44 / Chapter 4.5 --- Simulated Annealing --- p.45 / Chapter 4.6 --- Wirelength Estimation --- p.46 / Chapter 4.6.1 --- Center-to-center Estimation --- p.47 / Chapter 4.6.2 --- Corner-to-corner Estimation --- p.47 / Chapter 4.6.3 --- Intersection-to-intersection Estimation --- p.48 / Chapter 4.7 --- Multi-pin Nets Handling --- p.49 / Chapter 4.8 --- Experimental Results --- p.50 / Chapter 4.9 --- Summary --- p.51 / Chapter 5 --- Floorplanner with Flexible Buffer Planning [35] --- p.53 / Chapter 5.1 --- Introduction --- p.53 / Chapter 5.2 --- Overview of the Floorplanner --- p.54 / Chapter 5.3 --- Congestion Model --- p.55 / Chapter 5.3.1 --- Probabilistic Model with Variable Interval Buffer Inser- tion Constraint --- p.57 / Chapter 5.3.2 --- Time Complexity --- p.61 / Chapter 5.4 --- Buffer Planning --- p.62 / Chapter 5.4.1 --- Estimation of Buffer Usage --- p.62 / Chapter 5.4.2 --- Estimation of Buffer Resources --- p.69 / Chapter 5.5 --- Two-phases Simulated Annealing --- p.70 / Chapter 5.6 --- Wirelength Estimation --- p.72 / Chapter 5.7 --- Multi-pin Nets Handling --- p.73 / Chapter 5.8 --- Experimental Results --- p.73 / Chapter 5.9 --- Remarks --- p.76 / Chapter 5.10 --- Summary --- p.76 / Chapter 6 --- Global Router --- p.77 / Chapter 6.1 --- Introduction --- p.77 / Chapter 6.2 --- Overview of the Global Router --- p.77 / Chapter 6.3 --- Buffer Insertion Constraint and Congestion Constraint --- p.78 / Chapter 6.4 --- Multi-pin Nets Handling --- p.79 / Chapter 6.5 --- Routing Methodology --- p.79 / Chapter 6.6 --- Implementation --- p.80 / Chapter 6.7 --- Summary --- p.86 / Chapter 7 --- Interconnect-Driven Floorplanning by Alternative Packings --- p.87 / Chapter 7.1 --- Introduction --- p.87 / Chapter 7.2 --- Overview of the Method --- p.87 / Chapter 7.3 --- Searching Alternative Packings --- p.89 / Chapter 7.3.1 --- Rectangular Supermodules in Sequence Pair --- p.89 / Chapter 7.3.2 --- Finding rearrangable module sets --- p.90 / Chapter 7.3.3 --- Alternative Sequence Pairs --- p.94 / Chapter 7.4 --- Implementation --- p.97 / Chapter 7.4.1 --- Re-calculation of Interconnect Cost --- p.98 / Chapter 7.4.2 --- Cost Function --- p.101 / Chapter 7.4.3 --- Time Complexity --- p.101 / Chapter 7.5 --- Experimental Results --- p.101 / Chapter 7.6 --- Summary --- p.103 / Chapter 8 --- Conclusion --- p.105 / Bibliography --- p.107

Law Hoi Ying. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 101-106). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Cycle --- p.2 / Chapter 1.2 --- Physical Design Cycle --- p.6 / Chapter 1.3 --- Floorplanning --- p.10 / Chapter 1.3.1 --- Floorplanning Objectives --- p.11 / Chapter 1.3.2 --- Common Approaches --- p.12 / Chapter 1.3.3 --- Interconnect-Driven Floorplanning --- p.14 / Chapter 1.4 --- Motivations and Contributions --- p.15 / Chapter 1.5 --- Organization of the Thesis --- p.17 / Chapter 2 --- Literature Review on 2D Floorplan Representations --- p.18 / Chapter 2.1 --- Types of Floorplans --- p.18 / Chapter 2.2 --- Floorplan Representations --- p.20 / Chapter 2.2.1 --- Slicing Floorplan --- p.21 / Chapter 2.2.2 --- Non-slicing Floorplan --- p.22 / Chapter 2.2.3 --- Mosaic Floorplan --- p.30 / Chapter 2.3 --- Summary --- p.35 / Chapter 3 --- Literature Review on 3D Floorplan Representations --- p.37 / Chapter 3.1 --- Introduction --- p.37 / Chapter 3.2 --- Problem Formulation --- p.38 / Chapter 3.3 --- Previous Work --- p.38 / Chapter 3.4 --- Summary --- p.42 / Chapter 4 --- Literature Review on Bus-Driven Floorplanning --- p.44 / Chapter 4.1 --- Problem Formulation --- p.44 / Chapter 4.2 --- Previous Work --- p.45 / Chapter 4.2.1 --- Abutment Constraint --- p.45 / Chapter 4.2.2 --- Alignment Constraint --- p.49 / Chapter 4.2.3 --- Bus-Driven Floorplanning --- p.52 / Chapter 4.3 --- Summary --- p.53 / Chapter 5 --- Multi-Bend Bus-Driven Floorplanning --- p.55 / Chapter 5.1 --- Introduction --- p.55 / Chapter 5.2 --- Problem Formulation --- p.56 / Chapter 5.3 --- Methodology --- p.57 / Chapter 5.3.1 --- Shape Validation --- p.58 / Chapter 5.3.2 --- Bus Ordering --- p.65 / Chapter 5.3.3 --- Floorplan Realization --- p.72 / Chapter 5.3.4 --- Simulated Annealing --- p.73 / Chapter 5.3.5 --- Soft Block Adjustment --- p.75 / Chapter 5.4 --- Experimental Results --- p.75 / Chapter 5.5 --- Summary --- p.77 / Chapter 6 --- Bus-Driven Floorplanning for 3D Chips --- p.80 / Chapter 6.1 --- Introduction --- p.80 / Chapter 6.2 --- Problem Formulation --- p.81 / Chapter 6.3 --- The Representation --- p.82 / Chapter 6.3.1 --- Overview --- p.82 / Chapter 6.3.2 --- Review of TCG --- p.83 / Chapter 6.3.3 --- Layered Transitive Closure Graph (LTCG) --- p.84 / Chapter 6.3.4 --- Aligning Blocks --- p.85 / Chapter 6.3.5 --- Solution Perturbation --- p.87 / Chapter 6.4 --- Simulated Annealing --- p.92 / Chapter 6.5 --- Soft Block Adjustment --- p.92 / Chapter 6.6 --- Experimental Results --- p.93 / Chapter 6.7 --- Summary --- p.94 / Chapter 6.8 --- Acknowledgement --- p.95 / Chapter 7 --- Conclusion --- p.99 / Bibliography --- p.101

Cheung, Cheuk Kit. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references. / Abstract also in Chinese. / Abstract --- p.1 / 摘要 --- p.2 / Acknowledgements --- p.3 / Table of Contents --- p.4 / List of Figures --- p.9 / Chapter 1. --- Introduction --- p.12 / Chapter 1.1. --- Research Motivation --- p.12 / Chapter 1.1.1. --- Global and Intermediate Interconnects --- p.12 / Chapter 1.1.2. --- Constraints of Repeater Insertion Techniques --- p.13 / Chapter 1.2. --- Research Objective --- p.13 / Chapter 1.3. --- Reference --- p.14 / Chapter 2. --- Voltage Mode and Current Mode Circuits --- p.16 / Chapter 2.1. --- Introduction --- p.16 / Chapter 2.2. --- Voltage Mode Circuit --- p.16 / Chapter 2.3. --- Current Mode Circuit --- p.18 / Chapter 2.4. --- Power Consumption --- p.19 / Chapter 2.5. --- Latency --- p.20 / Chapter 2.6. --- Summary --- p.20 / Chapter 3. --- Transmitter Design --- p.22 / Chapter 3.1. --- Introduction --- p.22 / Chapter 3.2. --- Multi-level Signaling --- p.22 / Chapter 3.3. --- Gated Current Mirror --- p.23 / Chapter 3.4. --- Power Consumption --- p.24 / Chapter 3.5. --- Summary --- p.24 / Chapter 3.6. --- Reference --- p.25 / Chapter 4. --- Receiver Design --- p.26 / Chapter 4.1. --- Introduction --- p.26 / Chapter 4.2. --- Conventional Latched-typed Sense Amplifier --- p.27 / Chapter 4.3. --- Sense Amplifier with Isolated Differential Pair --- p.29 / Chapter 4.4. --- "Power Consumption, Latency and Kick-back Noise Comparison between Different Designs" --- p.30 / Chapter 4.4.1. --- Comparison on Power Consumption --- p.30 / Chapter 4.4.2. --- Comparison on Latency --- p.31 / Chapter 4.4.3. --- Comparison on Kick-back Noise --- p.33 / Chapter 4.5. --- Summary --- p.34 / Chapter 4.6. --- Reference --- p.34 / Chapter 5. --- Inverter Chain --- p.36 / Chapter 5.1. --- Introduction --- p.36 / Chapter 5.2. --- Inverter Chain Based --- p.36 / Chapter 5.3. --- Summary --- p.38 / Chapter 5.4. --- References --- p.38 / Chapter 6. --- Layout Techniques --- p.39 / Chapter 6.1. --- Introduction --- p.39 / Chapter 6.2. --- Two-Dimensional Common Centroid Layout Technique --- p.39 / Chapter 6.3. --- Dummy Devices --- p.40 / Chapter 6.4. --- Summary --- p.42 / Chapter 6.5. --- References --- p.42 / Chapter 7. --- Simulation Results --- p.43 / Chapter 7.1. --- Introduction --- p.43 / Chapter 7.2. --- Simulation of Different Aspect Ratios of Differential Pair --- p.43 / Chapter 7.3. --- System Level Simulation with Different Sense-amplifiers --- p.46 / Chapter 7.4. --- System Level Simulation at Different Data Rate --- p.47 / Chapter 7.5. --- Summary --- p.49 / Chapter 8. --- Measurement Results --- p.50 / Chapter 8.1. --- Introduction --- p.50 / Chapter 8.2. --- Experimental Setup --- p.50 / Chapter 8.2.1. --- Testing Chips --- p.50 / Chapter 8.2.2. --- Equipments Setup --- p.52 / Chapter 8.3. --- Measurement Results --- p.53 / Chapter 8.4. --- Summary --- p.56 / Chapter 9. --- Conclusion --- p.57 / Chapter 9.1. --- Author´ةs Contributions --- p.57 / Chapter 9.2. --- Future Works --- p.58 / Chapter 10. --- Appendix --- p.59

Leung, Chi Kwan. / Thesis submitted in: December 2007. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 66-68). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Literature Review on Fixed-outline Floorplanning --- p.5 / Chapter 2.1 --- General Floorplanning --- p.5 / Chapter 2.1.1 --- Simulated Annealing --- p.6 / Example - Normalized Polish Expression --- p.9 / Example - Sequence Pair Representation --- p.15 / Example - Corner Block List --- p.19 / Chapter 2.1.2 --- Genetic Algorithm --- p.24 / Chapter 2.1.3 --- Mixed Integer Linear Programming --- p.25 / Chapter 2.1.4 --- Geometric Programming --- p.25 / Chapter 2.1.5 --- Discussion --- p.26 / Advantages of using Simulated Annealing --- p.26 / Disadvantages of using Simulated Annealing --- p.27 / Chapter 2.2 --- Fixed-outline Floorplanning --- p.28 / Chapter 2.2.1 --- Motivation --- p.28 / Chapter 2.2.2 --- Dimension Based Cost Function --- p.30 / Chapter 2.2.3 --- Aspect Ratio Based Cost Function --- p.32 / Chapter 2.2.4 --- Evolutionary Search --- p.33 / Chapter 2.2.5 --- Instance Augmentation --- p.35 / Chapter 3 --- Predictive Rating with Fixed Outline Constraints --- p.39 / Chapter 3.1 --- Introduction --- p.39 / Chapter 3.2 --- Motivation --- p.40 / Chapter 3.3 --- Predictive Rating Scheme --- p.44 / Chapter 3.3.1 --- Area --- p.45 / Chapter 3.3.2 --- Dimensions --- p.46 / Chapter 3.3.3 --- Aspect Ratio --- p.47 / Chapter 3.3.4 --- Overall Equation for Predictive Rating --- p.48 / Chapter 3.4 --- Integration into the Floorplanner --- p.49 / Chapter 3.5 --- Experimental Results --- p.50 / Chapter 3.5.1 --- Accuracy of Predictive Rating --- p.50 / Chapter 3.5.2 --- Test One --- p.52 / Chapter 3.5.3 --- Test Two --- p.57 / Chapter 3.6 --- Conclusion --- p.61 / Chapter 4 --- Conclusion --- p.64 / Bibliography --- p.66

Jiang, Yan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (p. 87-92). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Physical Design --- p.2 / Chapter 1.2 --- Floorplanning --- p.6 / Chapter 1.2.1 --- Floorplanning Objectives --- p.7 / Chapter 1.2.2 --- Common Approaches --- p.8 / Chapter 1.3 --- Motivations and Contributions --- p.14 / Chapter 1.4 --- Organization of the Thesis --- p.15 / Chapter 2 --- Literature Review on BDF --- p.17 / Chapter 2.1 --- Zero-Bend BDF --- p.17 / Chapter 2.1.1 --- BDF Using the Sequence-Pair Representation --- p.17 / Chapter 2.1.2 --- Using B*-Tree and Fast SA --- p.20 / Chapter 2.2 --- Two-Bend BDF --- p.22 / Chapter 2.3 --- TCG-Based Multi-Bend BDF --- p.25 / Chapter 2.3.1 --- Placement Constraints for Bus --- p.26 / Chapter 2.3.2 --- Bus Ordering --- p.28 / Chapter 2.4 --- Bus-Pin-Aware BDF --- p.30 / Chapter 2.5 --- Summary --- p.33 / Chapter 3 --- Fixed-Outline BDF --- p.35 / Chapter 3.1 --- Introduction --- p.35 / Chapter 3.2 --- Problem Formulation --- p.36 / Chapter 3.3 --- The Overview of Our Approach --- p.36 / Chapter 3.4 --- Partitioning --- p.37 / Chapter 3.4.1. --- The Overview of Partitioning --- p.38 / Chapter 3.4.2 --- Building a Hypergraph G --- p.39 / Chapter 3.5 --- Floorplaiining with Bus Routing --- p.43 / Chapter 3.5.1 --- Find Bus Routes --- p.43 / Chapter 3.5.2 --- Realization of Bus Routes --- p.48 / Chapter 3.5.3 --- Details of the Annealing Process --- p.50 / Chapter 3.6 --- Handle Fixed-Outline Constraints --- p.52 / Chapter 3.7 --- Bus Layout --- p.52 / Chapter 3.8 --- Experimental Results --- p.56 / Chapter 3.9 --- Summary --- p.61 / Chapter 4 --- Fixed-Outline BDF with L-shape bus --- p.63 / Chapter 4.1 --- Introduction --- p.63 / Chapter 4.2 --- Problem Formulation --- p.64 / Chapter 4.3 --- Our Approach --- p.65 / Chapter 4.3.1 --- Bus Routability Checking --- p.67 / Chapter 4.3.2 --- Details of the Annealing Process --- p.79 / Chapter 4.4 --- Experimental Results --- p.79 / Chapter 4.5 --- Summary --- p.82 / Chapter 5 --- Conclusion --- p.85 / Bibliography --- p.92