Emerging I/O density and bandwidth requirements are driving packages to low-CTE silicon, glass and organic substrates for higher wiring density and reliability of interconnections and Cu-low k dielectrics. These are needed for high performance applications as 2.5D packages in large-size, and also as ultra-thin packages for consumer applications that are directly assembled on the board without the need for an intermediate package. The trend to low-CTE packages (CTE of 3-8ppm/°C), however, creates large CTE mismatch with the board on which they are assembled. Interconnection reliability is, therefore, a major concern when low CTE interposers are surface mounted onto organic system boards via solder joints. This reliability concern is further aggravated with large package sizes and finer pitch. For wide acceptance of low CTE packages in high volume production, it is also critical to assemble them on board using standard Surface Mount Technologies (SMT) without the need for under-fill. This research aims to demonstrate reliable 400 micron pitch solder interconnections from low CTE glass interposers directly assembled onto organic boards by overcoming the above challenges using two approaches; 1) Stress-relief dielectric build up layers on the back of the interposer, 2) Polymer collar around the solder bumps for shear stress re-distribution. A comprehensive methodology based on modeling, design, test vehicle fabrication and characterization is employed to study and demonstrate the efficacy of these approaches in meeting the interposer-to-board interconnection requirements. The effect of varying geometrical and material properties of both build-up layers and polymer collar is studied through Finite Element Modeling. Interposers were designed and fabricated with the proposed approaches to demonstrate process feasibility.

The main objective of this dissertation is to investigate a design methodology that can characterize and compensate for process and temperature variation. First, a design methodology is discussed to handle process variation in low-power memory for image processing application. This is followed by a design technique to characterize and recover TSV-defect-induced signal degradation in a 3D integrated circuit. For thermal variation, the spatiotemporal power migration is proposed as a methodology to handle thermal issues in digital systems both during the test and normal operation. The power migration continuously distributes the generated heat in space and time to control chip temperature. To enable this approach a unique method is developed, and verified through hardware for post-fabrication characterization of thermal system and prediction of transient variation in chip temperature. The inverse temperature dependence in a digital logic is characterized through hardware to help better thermal management in wide operating voltage design.

As operating frequency increases and device sizes shrink, the complexity of current state-of-the-art designs has increased dramatically. One of the main contributors to this complexity is high speed interconnects. At high frequencies, interconnects become dominant contributors to signal degradation, and their effects such as delays, reflections, and crosstalk must be accurately simulated. Time domain analysis of such structures is however very difficult because, at high frequencies, they must be modeled as distributed transmission lines which, after discretization, result in very large networks. In order to improve the simulation efficiency of such structures, model order reduction has been proposed in the literature. Conventional model order reduction methods based on Krylov subspace have a number of limitations in many practical simulation problems. This restricts their usefulness in general commercial simulators. / In this thesis, a number of new reduction techniques were developed in order to address the key shortcomings of current model order reduction methods. Specifically a new approach for handling macromodels with a very large number of ports was developed, a multi-level reduction and sprasification method was proposed for regular as well as parametric macromodels, and finally a new time domain reduction method was presented for the macromodeling of nonlinear parametric systems. Using these approaches, CPU speedups of 1 to 2 orders of magnitude were obtained.

Wires have become a major source of bottleneck in current VLSI designs, and wire length prediction is therefore essential to overcome these bottlenecks. Wire length prediction is broadly classified into two types: macroscopic prediction, which is the prediction of wire length distribution, and microscopic prediction, which is the prediction of individual wire lengths. The objective of this thesis is to develop a clear understanding of limitations to both macroscopic and microscopic a priori, post-placement, pre-routing wire length predictions, and thereby develop better wire length prediction models. Investigations carried out to understand the limitations to macroscopic prediction reveal that, in a given design (i) the variability of the wire length distribution increases with length and (ii) the use of Rent s rule with a constant Rent s exponent p, to calculate the terminal count of a given block size, limits the accuracy of the results from a macroscopic model. Therefore, a new model for the parameter p is developed to more accurately reflect the terminal count of a given block size in placement, and using this, a new more accurate macroscopic model is developed. In addition, a model to predict the variability is also incorporated into the macroscopic model. Studies to understand limitations to microscopic prediction reveal that (i) only a fraction of the wires in a given design are predictable, and these are mostly from shorter nets with smaller degrees and (ii) the current microscopic prediction models are built based on the assumption that a single metric could be used to accurately predict the individual length of all the wires in a design. In this thesis, an alternative microscopic model is developed for the predicting the shorter wires based on a hypothesis that there are multiple metrics that influence the length of the wires. Three different metrics are developed and fitted into a heuristic classification tree framework to provide a unified and more accurate microscopic model.

The fundamental motivation for this dissertation is to address the widening interconnect gap between integrated circuit (IC) demands and package substrates specifically for high frequency digital-RF systems applications. Moore's law for CMOS ICs predicts that transistor density on ICs will double approximately every 18 months. The current state-of-the-art in IC package substrates is at 20µm lines/spaces and 50-60µm microvia diameter using epoxy dielectrics with loss tangent above 0.01. The research targets are to overcome the barriers of current technologies and demonstrate a set of advanced materials and process technologies capable of 5-10µm lines and spaces, and 10-30µm diameter microvias in a multilayer 3-D wiring substrate using 10-25µm thin film dielectrics with loss tangent in the <0.005. The research elements are organized as follows with a clear focus on understanding and characterization of fundamental materials structure-processing-property relationships and interfaces to achieve the next generation targets. (a) Low CTE Core Substrate, (b) Low Loss Dielectrics with 25µm and smaller microvias, (c) Sub-10µm Width Cu Conductors, and (d) Integration of the various dielectric and conductor processes.

In this work, all-copper connections between silicon microchips and substrates are developed. The semiconductor industry advances the transistor density on a microchip based on the roadmap set by Moore's Law. Communicating with a microprocessor which has nearly one billion transistors is a daunting challenge. Interconnects from the chip to the system (i.e. memory, graphics, drives, power supply) are rapidly growing in number and becoming a serious concern. Specifically, the solder ball connections that are formed between the chip itself and the package are challenging to make and still have acceptable electrical and mechanical performance. These connections are being required to increase in number, increase in power current density, and increase in off-chip operating frequency. Many of the challenges with using solder connections are limiting these areas. In order to advance beyond the limitations of solder for electrical and mechanical performance, a novel approach to creating all-copper connections from the chip-to-substrate has been developed. The development included characterizing the electroless plating and annealing process used to create the connections, designing these connections to be compatible with the stress requirements for fragile low-k devices, and finally by improving the plating/annealing process to become process time competitive with solder. It was found that using a commercially available electroless copper bath for the plating, followed by annealing at 180 C for 1 hour, the shear strength of the copper-copper bond was approximately 165 MPa. This work resulted in many significant conclusions about the mechanism for bonding in the all-copper process and the significance of materials and geometry on the mechanical design for these connections.

Driven by the need for increase in system¡¯s functionality and decrease in the feature size, International Technology Roadmap for Semi-conductors has predicted that integrated chip packages will have interconnections with I/O pitch of 90 nm by the year 2018. Lead-based solder materials that have been used for many decades will not be able to satisfy the thermal mechanical requirements of these fines pitch packages. Of all the known interconnect technologies, nanostructured copper interconnects are the most promising for meeting the high performance requirements of next generation devices. However, there is a need to understand their material properties, deformation mechanisms and microstructural stability. The goal of this research is to study the mechanical strength and fatigue behavior of nanocrystalline copper using atomistic simulations and to evaluate their performance as nanostructured interconnect materials. The results from the crack growth analysis indicate that nanocrystalline copper is a suitable candidate for ultra-fine pitch interconnects applications. This study has also predicts that crack growth is a relatively small portion of the total fatigue life of interconnects under LCF conditions. The simulations result conducted on the single crystal copper nano-rods show that its main deformation mechanism is the nucleation of dislocations. In the case of nanocrystalline copper, material properties such as elastic modulus and yield strength have been found to be dependent on the grain size. Furthermore, it has been shown that there is competition between the dislocation activity and grain boundary sliding as the main deformation mode This research has shown that stress induced grain coarsening is the main reason for loss of mechanical performance of nanocrystalline copper during cyclic loading. Further, the simulation results have also shown that grain growth during fatigue loading is assisted by the dislocation activity and grain boundary migration. A fatigue model for nanostructured interconnects has been developed in this research using the above observations Lastly, simulations results have shown that addition of the antimony into nanocrystalline copper will not only increase the microstructure stability, it will also increase its strength.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Computer Science, Thomas J. Watson School of Engineering and Applied Science, 2007. / Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2008. / Includes bibliographical references.