Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

As multistep, multilayer processing in semiconductor industry becomes more complex, the role of cleaning solutions and etching chemistries are becoming important in enhancing yield and in reducing defects. This thesis demonstrates successful formulations that exhibit copper and tungsten compatibility, and are capable of Inter Layer Dielectric (ILD) cleaning and selective Ti etching. The corrosion behavior of electrochemically deposited copper thin films in deareated and non-dearated cleaning solution containing hydrofluoric acid (HF) has been investigated. Potentiodynamic polarization experiments were carried out to determine active, active-passive, passive, and transpassive regions. Corrosion rates were calculated from tafel slopes. ICP-MS and potentiodynamic methods yielded comparable Cu dissolution rates. Interestingly, the presence of hydrogen peroxide in the cleaning solution led to more than an order of magnitude suppression of copper dissolution rate. We ascribe this phenomenon to the formation of interfacial CuO which dissolves at slower rate in dilute HF. A kinetic scheme involving cathodic reduction of oxygen and anodic oxidation of Cu0 and Cu+1 is proposed. It was determined that the reaction order kinetics is first order with respect to both HF and oxygen concentrations. The learnings from copper corrosion studies were leveraged to develop a wet etch/clean formulation for selective titanium etching. The introduction of titanium hard-mask (HM) for dual damascene patterning of copper interconnects created a unique application in selective wet etch chemistry. A formulation that addresses the selectivity requirements was not available and was developed during the course of this dissertation. This chemical formulation selectively strips Ti HM film and removes post plasma etch polymer/residue while suppressing the etch rate of tungsten, copper, silicon oxide, silicon carbide, silicon nitride, and carbon doped silicon oxide. Ti etching selectivity exceeding three orders of magnitude was realized. Surprisingly, it exploits the use of HF, a chemical well known for its SiO2 etching ability, along with a silicon precursor to protect SiO2. The ability to selectively etch the Ti HM without impacting key transistor/interconnect components has enabled advanced process technology nodes of today and beyond. This environmentally friendly formulation is now employed in production of advanced high-performance microprocessors and produced in a 3000 gallon reactor.

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Major challenges in maintaining quality and reliability in today’s microelectronics devices come from the ever increasing level of integration in the device fabrication, as well as the high level of current densities that are carried through the microchip during operation. In order to have a framework for design and reliability assessment, it is imperative to develop a predictive capability for the thermal response of micro-electronic components. A computationally efficient and accurate multi-scale transient thermal methodology was developed using a combination of two different approaches: “Progressive Zoom-in” method and “Proper Orthogonal Decomposition (POD)” technique. The proposed technique has the capability of handling several decades of length scale from tens of millimeter at “package” level to several nanometers at “interconnects” level at a considerably lower computational cost, while maintaining satisfactory accuracy. This ability also applies for time scales from seconds to microseconds corresponding to various transient thermal events. The proposed method also provides the ability to rapidly predict thermal responses under different power input patterns, based on only a few representative detailed simulations, without compromising the desired spatial and temporal resolutions. It is demonstrated that utilizing the proposed model, the computational time is reduced by at least two orders of magnitude at every step of modeling. Additionally, a novel experimental platform was developed to evaluate rapid transient Joule heating in embedded nanoscale metallic films representing buried on-chip interconnects that are not directly accessible. Utilizing the state-of-the-art sub-micron embedded resistance thermometry the effect of rapid transient power input profiles with different amplitudes and frequencies were studied. It is also demonstrated that a spatial resolution of 6 µm and thermal time constant of below 1 µs can be achieved using this technique. Ultimately, the size effects on the thermal and material properties of embedded metallic films were studied. A state-of-the-art technique to extract thermal conductivity of embedded nanoscale interconnects was developed. The proposed structure is the first device that has enabled the conductivity measurement of embedded metallic films on a substrate. It accounts for the effect of the substrate and interface without compromising the sensitivity of the device to the thermal conductivity of the metallic film. Another advantage of the proposed technique is that it can be integrated within the structure and be used for measurements of embedded or buried structures such as nanoscale on chip interconnects, without requiring extensive micro-fabrication. The dependence of the thermal conductivity on temperature was also investigated. The experimentally measured values for thermal conductivity and its dependence on temperature agree well with previous studies on free-standing nanoscale metallic bridges.

Fourier telescopy imaging is a recently-developed imaging method that relies on active structured-light illumination of the object. Reflected/scattered light is measured by a large “light bucket” detector; processing of the detected signal yields the magnitude and phase of spatial frequency components of the object reflectance or transmittance function. An inverse Fourier transform results in the image. In 2012 a novel method, known as time-average Fourier telescopy (TAFT), was introduced by William T. Rhodes as a means for diffraction-limited imaging through ground-level atmospheric turbulence. This method, which can be applied to long horizontal-path terrestrial imaging, addresses a need that is not solved by the adaptive optics methods being used in astronomical imaging. Field-experiment verification of the TAFT concept requires instrumentation that is not available at Florida Atlantic University. The objective of this doctoral research program is thus to demonstrate, in the absence of full-scale experimentation, the feasibility of time-average Fourier telescopy through (a) the design, construction, and testing of smallscale laboratory instrumentation capable of exploring basic Fourier telescopy datagathering operations, and (b) the development of MATLAB-based software capable of demonstrating the effect of kilometer-scale passage of laser beams through ground-level turbulence in a numerical simulation of TAFT. / Includes bibliography. / Dissertation (Ph.D.)--Florida Atlantic University, 2015. / FAU Electronic Theses and Dissertations Collection

Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function. The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance. Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and blocks, as well as nets-to-TSVs assignment to obtain floorplans with minimized coupling noise. We also suggested diagonal TSV arrangement for larger TSV pitch and nonuniform pitch arrangement for reducing worst TSV-to-TSV coupling, thereby minimizing the coupling noise in the interconnects. This thesis also focuses on more realistic evaluation and optimization of delay and power in TSV based 3D integrated circuits considering the interconnect density on individual device layers. The floorplanning tool uses TSV locations and delay, non-uniform interconnect density across multiple stacked device layers to assess and optimize the buffer count, delay, and interconnect power dissipation in a design. It is shown that the impact of non-uniform interconnect density, across the stacked device layers, should not be ignored, as its contribution to the performance of the 3D interconnects is consequential. A wire capacitance-aware buffer insertion scheme is presented that determines the optimal distance between adjacent buffers on the individual device layers for nonuniform wire density between stacked device layers. The proposed approach also considers TSV location on a 3D wire to optimize the buffer insertion around TSVs. For 3D designs with uniform wire density across stacked device layers, we propose a TSV-aware buffer insertion approach that appropriately models the TSV RC delay impact on interconnect delay to determine the optimum interval between adjacent buffers for individual 3D nets. Moreover, our floorplanning tool help achieve 3D layouts with superior performance by incorporating the impact of nonuniform density on the delay, power and coupling noise in the interconnects during floorplanning.

Isotropically conductive adhesives (ICAs) are promising as a lead-free interconnect material; However, ICAs have a higher resistivity compared to tin/lead solder. The higher resistivity of ICAs results from the large contact resistance between conductive fillers. Several novel approaches to engineer the interface between electrically conductive fillers were studied to develop highly conductive ICAs. Shown in this dissertation are three methodologies to reduce contact resistance: low temperature sintering, fast sintering and in-situ reduction. Furthermore, two approaches, surface modification and in-situ protection, were developed to prevent oxidation and corrosion of silver-coated copper flakes to produce low cost ICAs. The findings and insights in this dissertation significantly contribute to (1) understanding of filler-filler, filler-polymer and structure-property relationships of ICAs; (2) the structural design and formulation of high performance ICAs; and (3) the wider use of ICAs in emerging applications such as printed electronics and solar cells.

The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs. The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength. The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance. The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness. The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated. The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs.

Conventional solder balls used in microelectronic packaging suffer from thermo- mechanical damage due to difference in coefficient of thermal expansion between the die and the substrate or the substrate and the board. Compliant interconnects are replacements for solder balls which accommodate this differential displacement by mechanically decoupling the die from the substrate or the substrate from the board and aim to improve overall reliability and life of the microelectronic component. Research is being conducted to develop compliant interconnect structures which offer good mechanical compliance without adversely affecting electrical performance, thus obtaining good thermo-mechanical reliability. However, little information is available regarding the behavior of compliant interconnects under shock and impact loads. The objective of this thesis is to study the response of a proposed multi-path compliant interconnect structure when subjected to shock and impact loading. As part of this work, scaled-up substrate-compliant interconnect-die assemblies will be fabricated through stereolithography techniques. These scaled-up prototypes will be subjected to experimental drop testing. Accelerometers will be placed on the board, and strain gauges will be attached to the board and the die at various locations. The samples will be dropped from different heights to different shock levels in the components, according to Joint Electron Devices Engineering Council (JEDEC) standards. In parallel to such experiments with compliant interconnects, similar experiments with scaled-up solder bump interconnects will also be conducted. The strain and acceleration response of the compliant interconnect assemblies will be compared against the results from solder bump interconnects. Simulations will also be carried out to mimic the experimental conditions and to gain a better understanding of the overall response of the compliant interconnects under shock and impact loading. The findings from this study will be helpful for improving the reliability of compliant interconnects under dynamic mechanical loading.