This thesis is devoted to the research and development of low processing temperature lead-free interconnect materials for microelectronic packaging applications with an emphasis on fundamental studies of nanoparticles synthesis, dispersion and oxidation prevention, and nanocomposites fabrication. Oxide-free tin (Sn), tin/silver (96.5Sn3.5Ag) and tin/silver/copper (96.5Sn3.0Ag0.5Cu) alloy nanoparticles with different sizes were synthesized by a low temperature chemical reduction method. Both size dependent melting point and latent heat of fusion of the synthesized nanoparticles were obtained. The nano lead-free solder pastes/composites created by dispersing the SnAg or SnAgCu alloy nanoparticles into an acidic type flux spread and wet on the cleaned copper surface at 220 to 230 ¡æ. This study demonstrated the feasibility of nano sized SnAg or SnAgCu alloy particle pastes for low processing temperature lead-free interconnect applications in microelectronic packaging. Surface functionalized silver nanoparticles and silver fakes were used as fillers for electrically conductive adhesives (ECAs) applications. During the curing of epoxy resin (150 ¡æ), the surfactants were debonded from the particles and at the same time the oxide layers on the particle surfaces were removed which facilitated the sintering of Ag nanoparticles. The contact interfaces between fillers were significantly reduced and an ultra highly conductive ECA with a resistivity of 5 ¡Á 10-6 ohm.cm was obtained. To enhance the adhesion of carbon nanotube (CNT) films to substrates, an ultra highly conductive ECA were used as a media to transfer the CNT films to copper substrates. The polymer wetted along the CNTs during curing process by the capillary force. An ohmic contact was formed between the copper substrates and the transferred CNTs. This process could overcome the serious obstacles of integration of CNTs into integrated circuits and microelectronic device packages by offering low processing temperatures and improved adhesion of CNTs to substrates. The transferred CNTs can be used to simultaneously form electrical and mechanical connections between chips and substrates.

It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2019, with the IC feature size shrinking to about 10nm, off-chip interconnects in an area array format will require a pitch of 95 µm. Also, as the industry adopts porous low-K dielectric materials, it is important to ensure that the stresses induced by the off-chip interconnects and the package do not crack or delaminate the low-K material. Compliant free-standing structures used as off-chip interconnects are a potential solution. However, there are several design, fabrication, assembly and integration research challenges and gaps with the current suite of compliant interconnects. Accordingly, as part of this research a unique parallel-path approach has been developed which enhances the mechanical compliance of the compliant interconnect without compromising the electrical parasitics. It also provides for redundancy and thus results in more reliable interconnects. Also, to meet both electrical and mechanical performance needs, as part of this research a variable compliance approach has been developed so that interconnects near the center of the die have lower electrical parasitics while the interconnects near the corner of the die have higher mechanical compliance. Furthermore, this work has developed a fabrication process which will facilitate cost-effective fabrication of free-standing compliant interconnects and investigated key factors which impact assembly yield of free-standing compliant interconnects. Ultimately the proposed approaches are demonstrated by developing an innovative compliant interconnect called FlexConnects. Hence, through this research it is expected that the developed compliant interconnect would address the needs of first level interconnects over the next decade and eliminate a bottleneck that threatens to impede the exponential growth in microprocessor performance. Also, the concepts developed in this research are generic in nature and can be extended to other aspects of electronic packaging.

Electrically conductive adhesives (ECAs) are one of the lead-free interconnect materials with the advantages of environmental friendliness, mild processing conditions, fewer processing steps, low stress on the substrates, and fine pitch interconnect capability. However, some challenging issues still exist for the currently available ECAs, including lower electrical conductivity, conductivity fatigue in reliability tests, limited current-carrying capability, poor impact strength, etc. The interfacial properties is one of the major considerations when resolving these challenges and developing high performance conductive adhesives. Surface functionalization and interface modification are the major approaches used in this thesis. Fundamental understanding and analysis of the interaction between various types of interface modifiers and ECA materials and substrates are the key for the development of high performance ECA for lead-free interconnects. The results of this thesis provide the guideline for the enhancement of interfacial properties of metal-metal and metal-polymer interactions. Systematic investigation of various types of ECAs contributes to a better understanding of materials requirements for different applications, such as surface mount technology (SMT), flip chip applications, flat panel display modules with high resolution, etc. Improvement of the electrical, thermal and reliability of different ECAs make them a potentially ideal candidate for high power and fine pitch microelectronics packaging option.

As the convergence of multiple functions in a single electronic device drives current electronic trends, the need for increasing integration density is becoming more emphasized than in the past. To keep up with the industrial need and realize the new system integration law, three-dimensional (3-D) integration called System-on-Package (SoP) is becoming necessary. However, the commercialization of 3-D integration should overcome several technical barriers, one of which is the difficulty for the electrical design of interconnections. The 3-D interconnection design is difficult because of the modeling challenge of electrical coupling from the complicated structures of a large number of interconnections. In addition, mixed-signal design requires broadband modeling, which covers a large frequency spectrum for integrated microsystems. By using currently available methods, the electrical modeling of 3-D interconnections can be a very challenging task. This dissertation proposes a new method for constructing a broadband model of a large number of 3-D interconnections. The basic idea to address the many interconnections is using modal basis functions that capture electrical effects in interconnections. Since the use of global modal basis functions alleviates the need for discretization process of the interconnection structure, the computational cost is reduced considerably. The resultant interconnection model is a RLGC model that describes the broadband electrical behavior including losses and couplings. The smaller number of basis functions makes the interconnection model simpler, and therefore allows the generation of network parameters at reduced computational cost. Focusing on the modeling of bonding wires in stacked ICs and through-silicon via (TSV) interconnections, this research validates the interconnection modeling approach using several examples from 3-D full-wave EM simulation results.

Thesis (Ph. D.)--Ohio State University, 2005. / Title from first page of PDF file. Document formatted into pages; contains xvi, 136 p.; also includes graphics (some col.). Includes bibliographical references (p. 125-136). Available online via OhioLINK's ETD Center

This thesis contains 2 parts (Part A and B) to fulfill the requirements for the degree of Master of Engineering. Part A: McMaster (on-campus) project. Part B: McMaster (industrial) project. / Part A abstract: The demodulation of analogue F.M. signals using frequency counting techniques is examined and implemented through the use of modern high speed T.T.L. integrated circuit technology. The entire demodulation unit was derived from exclusively digital components particularly compatible to frequency counting methods. The device was tested with carrier frequencies up to 2MHz and signal frequencies over the entire audio range with varying degrees of modulation. The main limitations appear to lay not in the hardware but in the actual counting technique itself which required quite large frequency deviations to resolve the higher audio frequency signals employed. Part B abstract: Investigation of SnO(2):B:Sb semiconductor species over the temperature range -60°C to +175°C reveals that electrical resistivity in this region is determined by the complex superposition of stable thin film scattering phenomena. Transient effects due to lattice imperfections inherent in the fabrication process start to "anneal” out at temperatures greater than 50°c and can be characterized by an activation energy of the order of .013 eV. Uncompensated samples doped heavily with boron illustrate a trend toward ionized impurity scattering at lower temperatures but mainly the species exhibits a complicated interplay of acoustical and optical phonon scattering modulated by doping level in such a manner as to lower T.C.R. An empirical expression relating resistivity-temperature behaviour to doping is developed. / Thesis / Master of Engineering (ME)

The objective of this research is to demonstrate the impact of interconnect process variations, line-edge roughness and size effects on interconnect effective resistivity and ultimately chip performance. The investigation is accomplished through five tasks. In Task I, a new closed-form effective resistivity model, which is a function of line-edge roughness (LER), surface specularity and grain boundary reflectivity, is derived. In Task II, a critical path model is enhanced by including interconnect parasitics using the model in Task I. This enhancement also involves an extensive survey of foundry process data to shed light on the device resistance estimation used in the critical path model in Task II. Task III develops a Monte Carlo (MC) simulation framework called the Fast Interconnect Statistical Simulator (FISS). Using the latest International Technology Roadmap for Semiconductors (ITRS) projections, the FISS projects the impact of interconnect process variations and size effects onto high performance microprocessor units (HP-MPUs). Task IV fabricates metallic interconnect test structures with sub-100nm line-widths. The fifth task statistically calibrates the model from Task I using resistivity data measured from the test structures in Task IV.

The use of optical input/output (I/O) interconnects, in addition to electrical I/Os, is a promising approach for achieving high-bandwidth, chip-to-board communications required for future high-performance gigascale chip-based systems. While numerous efforts are underway to investigate the integration of optoelectronics and silicon microelectronics, virtually no work has been reported relating to testing of such chips. The objective of this research is to explore methods that enable wafer-level testing of gigascale chips having electrical and optical I/O interconnects. A major challenge in achieving this is to develop probe modules which would allow high-precision, temporary interconnection of a multitude of electrical and optical I/Os, in a chip-size area, to automated test equipment. A probe module would need to do this in a rapid, step-and-repeat manner across all the chips on the wafer. In this work, two candidate probe modules were devised, batch-fabricated on Si using microfabrication techniques, and successfully demonstrated. The first probe module consists of compliant electrical probes (10^3 probes/cm^2) fabricated alongside grating-in-waveguide optical probes. The second module consists of micro-opto-electro-mechanical-systems (MOEMS)-based microsocket probes (10^4 probes/cm^2) to interface a chip with polymer pillar-based electrical and optical I/Os. High-density through-wafer interconnects are an essential attribute in both probe substrates for transferring electrical and optical signals to the substrate back-side. Fabrication and characterization of metal-clad, metal-filled, and polymer-filled through-wafer interconnects as well as process integration with probe substrate fabrication are described and numerous possible redistribution schemes are explicated. Chips with optical and electrical I/Os are an emerging technology, and one that test engineers are likely to encounter in the near future. The contributions of this thesis are to help understand and address the issues relating to joint electrical and optical testing during manufacturing.

Recently, microelectronics designs have reached extremely high operating frequencies as well as very small die and package sizes. This has made signal integrity an important bottleneck in the design process, and resulted in the inclusion of signal integrity simulation in the computer aided design flow. However, such simulations are often difficult because in many cases it is impossible to derive analytical models for certain passive elements, and the only available data are frequency-domain measurements or full-wave simulations. Furthermore, at such high frequencies these components are distributed in nature and require a large number of poles to be properly characterized. Simple lumped equivalent circuits are therefore difficult to obtain, and more systematic approaches are required. In this thesis we study the Vector Fitting techniques for obtaining such equivalent model and propose a more streamlined approach for preserving passivity while maintaining accuracy.

The continuous miniaturization of electronic systems using the three-dimensional (3D) integration technique has brought in new challenges for the computer-aided design and modeling of 3D integrated circuits (ICs) and systems. The major challenges for the modeling and analysis of 3D integrated systems mainly stem from four aspects: (a) the interaction between the electrical and thermal domains in an integrated system, (b) the increasing modeling complexity arising from 3D systems requires the development of multiscale techniques for the modeling and analysis of DC voltage drop, thermal gradients, and electromagnetic behaviors, (c) efficient modeling of microfluidic cooling, and (d) the demand of performing fast thermal simulation with varying design parameters. Addressing these challenges for the electrical/thermal modeling and analysis of 3D systems necessitates the development of novel numerical modeling methods. This dissertation mainly focuses on developing efficient electrical and thermal numerical modeling and co-simulation methods for 3D integrated systems. The developed numerical methods can be classified into three categories. The first category aims to investigate the interaction between electrical and thermal characteristics for power delivery networks (PDNs) in steady state and the thermal effect on characteristics of through-silicon via (TSV) arrays at high frequencies. The steady-state electrical-thermal interaction for PDNs is addressed by developing a voltage drop-thermal co-simulation method while the thermal effect on TSV characteristics is studied by proposing a thermal-electrical analysis approach for TSV arrays. The second category of numerical methods focuses on developing multiscale modeling approaches for the voltage drop and thermal analysis. A multiscale modeling method based on the finite-element non-conformal domain decomposition technique has been developed for the voltage drop and thermal analysis of 3D systems. The proposed method allows the modeling of a 3D multiscale system using independent mesh grids in sub-domains. As a result, the system unknowns can be greatly reduced. In addition, to improve the simulation efficiency, the cascadic multigrid solving approach has been adopted for the voltage drop-thermal co-simulation with a large number of unknowns. The focus of the last category is to develop fast thermal simulation methods using compact models and model order reduction (MOR). To overcome the computational cost using the computational fluid dynamics simulation, a finite-volume compact thermal model has been developed for the microchannel-based fluidic cooling. This compact thermal model enables the fast thermal simulation of 3D ICs with a large number of microchannels for early-stage design. In addition, a system-level thermal modeling method using domain decomposition and model order reduction is developed for both the steady-state and transient thermal analysis. The proposed approach can efficiently support thermal modeling with varying design parameters without using parameterized MOR techniques.