One-dimensional (1D) nanomaterial self-assembly offers an excellent approach to the fabrication of highly complex nanodevices. Despite considerable effort and research, precisely controlling the orientation and positioning of nanowires (NWs) on a large-scale area and assembling into a functional device is still a state of the art problem. This thesis focuses on the dimensionally controlled copper nanowires (Cu NWs) synthesis, and magnetic field assisted self-assembly of cupronickel nanowires (Cu/Ni NWs) into interconnect structures on a carbon doped silicon dioxide (CDO) wafer. CDO is a low dielectric constant (k) material used for copper interconnects in multilayered complex integrated circuits (ICs). Here, a strong affinity of copper (Cu) and nickel (Ni) to thiol (-SH) functional groups were exploited to strongly adhere the nanowires (Cu/Ni NWs) onto the CDO substrate. Thiol (-SH) functionalization of the CDO surface was achieved via a series of reactions involving (1) esterification of the surface exposed ≡Si-OH functional group to its triflate (≡Si-O-Tf), (2) reduction of triflate to ≡Si-H using DIBAL-H, and (3) hydrosilylation of ≡Si-H using 2-propene thiol (≡Si-(CH2)3-SH) in a photochemical reaction. The thiol functionalization of CDO surface enhances the interaction of Cu/Ni NWs with strong chemical bonds. The same reaction scheme was also used in the functionalization of the hydrophilic (Si-OH) surface to the hydrophobic long alkyl chain derivatized (≡Si-CH2-(CH2)16-CH3) surface. This long alkyl chain modified surface acts as an excellent moisture resistant film, which helps to maintain the low-k value of CDO. The dimensionally controlled Cu NWs were synthesized by a wet chemical approach. Optimization of the reducing agent, hydrazine (N2H4), controlled the surface morphology of nanowires (NWs). Interestingly, the high concentration of reducing agent produced particle decorated and/or with a rough NW surface, and conversely decreasing its concentration resulted in a comparatively thin, particle-free and smooth surface. The reaction temperature affected the aspect ratio (Length/Diameter) of the NWs. As the reaction temperature increased from 60 to 90 °C, the aspect ratio decreased from 140 to 21. Controlling the orientation of Cu NWs in a magnetic field was accomplished by coating them with a thin layer (~20 nm) of ferromagnetic nickel (Ni). This Ni-coated NWs showed an excellent degree of alignment (half-width ≈10 degrees) in the direction of an applied magnetic field over a large surface area at field strength as low as 2500 Gauss. Also, the Ni coating helped in protecting the copper core from oxidation resulting in better electrical wire-to-wire contacts. A nanowire-based interconnect channel was fabricated by combining magnetic field assisted alignment and deposition of aligned NWs on a thiol-modified and photolithography patterned CDO substrate. The NWs, deposited in the trenches, strongly bonded to the thiol-derivatized CDO substrate while an acetone wash removed loosely bound NWs on the photoresist surface. In electrical characterization, the directionally well-aligned Cu/Ni NWs channel displayed surprisingly two-fold higher conductivity than randomly arranged NWs channel.

"More Than Moore's Law" is the driving principle for the electronic packaging industry. This principle focuses on system integration instead of transistor density in order to achieve faster, thinner, and smarter electronic devices at a low cost. A core area of electronics packaging is interconnection technology, which enables ultra-miniaturization and high functional density. Solder bump technology is one of the original, and most common interconnection methods for flip chips. With growing demand for finer pitch and higher number of I/Os, solder bumps have been forced to smaller dimensions and therefore, are subjected to higher current densities. However, the technology is now reaching its fundamental limitations in terms of pitch, processability, and current-handling due to electromigration. Electromigration in solder bumps is one of the major causes of device failures. It is accelerated by many factors, one of which is current crowding. Current crowding is the non-uniform distribution of current at the interface of the solder bump and under-bump metallurgy, resulting in an increase in local current density and temperature. These factors, along with the formation of intermetallic compounds, can lead to voiding and ultimately failure. Electromigration in solder bumps has prevented pitch-scaling below 180-210 microns, producing a shift in the packaging industry to other interconnection approaches, specifically copper pillars with solder. This research aims to explore the electromigration resistance of an adhesive-based copper-to-copper (Cu-Cu) interconnection method without solder, which is thermo-compression bonded at a low temperature of 180C. While solder bumps are more susceptible to electromigration, Cu is capable of handling two orders of magnitude higher current density. This makes it an ideal candidate for next generation flip chip interconnections. Using finite element analysis, the current crowding and joule heating effects were evaluated for a 30 micron diameter Cu-Cu interconnection in comparison with two existing flip chip interconnection techniques, Cu pillar with solder and Pb-free solder. A test vehicle (TV) was fabricated for experimental analysis with 760 bumps arranged in an area-array format with a bump diameter of 30 micron. Thermo-mechanical reliability of the test vehicle was validated under thermal cycling from -55C to 125C. The Cu-Cu interconnections were then subjected to high current and temperature stress from 1E4 to 1E6 amps per square centimeter at a temperature of 130C. The results establish the high thermo-mechanical reliability and high electromigration resistance of the proposed Cu-Cu interconnection technology.

The interconnect fabric that provides electrical connectivity to active devices is an essential component to modern semiconductor chips. As the dimensions of these devices are scaled to improve performance and keep pace with Moore's Law, the local Cu interconnects must scale in parallel. Intrinsic material properties of Cu result in spiking electrical resistivity with scaling and present a looming bottleneck to chip performance. In this thesis, we introduce graphene as a replacement material to Cu interconnects in support of future chip scaling. In particular we focus on experimentally establishing fundamental mechanisms of chemically doping graphene via the basal plane and edge passivation, with broad contributions that extend beyond the focus of local interconnects.

Optical interconnects are important to the future development of microelectronics. Volume grating couplers (VGCs) provide a compact, efficient coupling mechanism that is compatible with microelectronics fabrication processes. In this dissertation, some of the performance characteristics of VGCs are investigated. Also, integration of VGCs with Sea of Polymer Pillars (SoPP), an emerging high-density input/output interconnect technology, is demonstrated and its performance quantitatively investigated. First, the polarization-dependent performance of VGCs is analyzed, and the design constraints for achieving high-efficiency polarization-dependent and polarization-independent VGCs are examined. The effects of loss on VGC performance are also presented. Then, the wavelength response of VGCs and its dependence on grating parameters is quantitatively examined. Experimental demonstrations of polarization-dependent and polarization-independent VGCs are then presented. Finally, a VGC integrated with a SoPP is demonstrated and its performance characterized.

As the complexity of interconnects and packages increases and the rise and fall time of the signal decreases, the electromagnetic effects of distributed passive devices are becoming an important factor in determining the performance of gigahertz systems. The electromagnetic behavior extracted using an electromagnetic simulation or from measurements is available as frequency dependent data. This information can be represented as a black box called a macromodel, which captures the behavior of the passive structure at the input/output ports. In this dissertation, the macromodels have been categorized as scalable, passive and broadband macromodels. The scalable macromodels for building design libraries of passive devices have been constructed using multidimensional rational functions, orthogonal polynomials and selective sampling. The passive macromodels for time-domain simulation have been constructed using filter theory and multiport passivity formulae. The broadband macromodels for high-speed simulation have been constructed using band division, selector, subband reordering, subband dilation and pole replacement. An automated construction method has been developed. The construction time of the multiport macromodel has been reduced. A method for reducing the order of the macromodel has been developed. The efficiency of the methods was demonstrated through embedded passive devices, known transfer functions and distributed interconnect networks.

Although copper (Cu) is the preferred interconnect material due to its lower resistivity than aluminum (Al), Cu subtractive etching processes have not been developed at temperatures less than 180 °C, primarily due to the inability to form volatile etch products at low temperature. The conventional damascene technology avoids the need for subtractive etching of Cu by electroplating Cu into previously etched dielectric trenches/vias, followed by a chemical/mechanical planarization (CMP) process. However, a critical "size effect" limitation has arisen for damascene technology as a result of the continuing efforts to adhere to "Moore's Law". The size effect relates to the fact that the resistivity of damascene-generated lines increases dramatically as the line width approaches the sub-100 nm regime, where feature size is similar to the mean free path of electrons in Cu (40 nm). As a result, an alternative Cu patterning process to that of damascene may offer advantages for device speed and thus operation. This thesis describes investigations into the development of novel, fully-plasma based etch processes for Cu at low temperatures (10 °C). Initially, the investigation of a two-step etch process has been studied. This etch approach was based on a previous thermodynamic analysis of the Cu-Cl-H system by investigators at the University of Florida. In the first step, Cu films are exposed to a Cl₂ plasma to preferentially form CuCl₂, which is believed to be volatilized as Cu₃Cl₃ by subsequent exposure to a hydrogen (H₂) plasma (second step). Patterning of Cu films masked with silicon dioxide (SiO₂) layers in an inductively coupled plasma (ICP) reactor indicates that the H₂ plasma step in the two-step process is the limiting step in the etch process. This discovery led to the investigation of a single step Cu etch process using a pure H₂ plasma. Etching of blanket Cu films and Cu film patterning at 10°C, display an etch rate ~ 13 nm/min; anisotropic etched features are also observed. Comparison of H₂ plasma etching to sputtering of Cu films in argon (Ar) plasmas, indicates that both a chemical component and a physical component are involved in the etching mechanism. Additional studies using helium plasmas and variation of power applied to the plasma and etching surface demonstrate that the etch rate is controlled by reactive hydrogen species, ion bombardment flux and likely photon flux. Optical Emission Spectroscopy (OES) of the H₂ plasma during the Cu etching process detects Cu emission lines, but is unable to identify specific Cu etch products that desorb from the etching surface. Variation of Cu etch rates as a function of temperature suggests a change in mechanism for the removal of Cu over the temperature of -150 °C to 150 °C. OES analyses also suggest that the Cl₂ plasma step in the two-step process can inhibit Cu etching, since the subsequent H₂ (second) plasma step shows a time delay in film removal. Preliminary results of the etching of the SiO₂ mask material in H₂ plasmas with various intentionally introduced contaminants demonstrate the robustness of the H₂ plasma Cu etch process.

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

Not available / text

The microelectronics industry has been managing the RC delay problem arising from aggressive line scaling, by replacing aluminum (Al) by copper (Cu) and oxide dielectric by low-k dielectric. Electromigration (EM) turned out to be a serious reliability problem for Cu interconnects due to the implementation of mechanically weaker low-k dielectrics. In addition, line width and via size scaling resulted in the need of a novel diffusion barrier, which should be uniform and thin. The objective of this dissertation is to investigate the impacts of Ta barrier process, such as barrier-first and pre-clean first, and scaling of barrier and line/via on EM reliability of Cu/low-k interconnects. For this purpose, EM statistical test structures, having different number of line segments, line width, and via width, were designed. The EM test structures were fabricated by a dualdamascene process with two metal layers (M1/Via/M2), which were then packaged for EM tests. The package-level EM tests were performed in a specially designed vacuum chamber with pure nitrogen environment. The novel barrier deposition process, called barrier-first, showed a higher (jL)[subscript c] product and prolonged EM lifetime, compared with the conventional Ta barrier deposition process, known as pre-clean first. This can be attributed to the improved uniformity and thickness of the Ta layer on the via and trench, as confirmed by TEM. As for the barrier thickness effect, the (jL)c product decreased with decreasing thickness, due to reduced Cu confinement. A direct correlation between via size and EM reliability was found; namely, EM lifetime and statistics degraded with via size. This can be attributed to the fact that critical void length to cause open circuit is about the size of via width. To investigate further line scaling effect on EM reliability, SiON (siliconoxynitride) trenchfilling process was introduced to fabricate 60-nm lines, corresponding to 45-nm technology, using a conventional, wider line lithograph technology. The EM lifetime of 60-nm fine lines with SiON filling was longer than that of a standard damascene structure, which can be attributed to a distinct via/metal-1 configuration in reducing process-induced defects at the via/metal-1 interface. / text

Microwave circuit design including the design of Interconnect circuits are proving to be a very hard and complex process where the use of CAD tools is becoming more essential to the reduction in design time and in providing more accurate results. Space mapping methods, the relatively new and very efficient way of optimization which are used in microwave filters and structures will be investigated in this thesis and applied to the time domain optimization of digital interconnects. The main advantage is that the optimization is driven using simpler models called coarse models that would approximate the more complex fine model of the real system, which provide a better insight to the problem and at the same time reduce the optimization time. The results are always mapped back to the real system and a relation/mapping is found between both systems which would help the convergence time. In this thesis, we study the optimization of interconnects where we build certain practical error functions to evaluate performance in the time domain. The space mapping method is formulated to avoid problems found in the original formulation where we apply some necessary modifications to the Trust Region Aggressive Space Mapping TRASM for it to be applicable to the design process in time domain. This new method modified TRASM or MTRASM is then evaluated and tested on multiple circuits with different configuration and the results are compared to the results obtained from TRASM.