Stress induced void formation in Cu interconnects, due to thermal stresses generated during the processing of semiconductors, is an increasing reliability issue in the semiconductor industry as Cu interconnects are being downscaled to follow the demand for faster chip speed. In this work, 1.8 micron and 180 nm wide Cu interconnects, fabricated by Freescale Semiconductors, were subjected to thermal cycles, in-situ in the TEM, to investigate the stress relaxation mechanisms as a function of interconnect linewidth. The experiments show that the 1.8 micron Cu interconnect lines relax the thermal stresses through dislocation nucleation and motion while the Cu interconnect 180 nm lines exhibit void formation. Void formation in 180 nm lines occurs predominantly at triple junctions where the Ta diffusion barrier meets a Cu grain boundary. In order to understand void formation in 180 nm lines, the grain orientation and local stresses are determined. In particular, Nanobeam Diffraction (NBD) in the TEM is used to obtain the diffraction pattern of each grain, from which the crystal orientation is evaluated by the ACT (Automated Crystallography for TEM) software. In addition, 2D Finite Element Method (FEM) simulations are performed using the Object Oriented Finite Modeling (OOF2) software to correlate grain orientation with local stresses, and consequently void formation. According to the experimental and simulation results obtained, void formation in 180nm Cu interconnects does not seem to be solely dependent on local stresses, but a combination of diffusion paths available, stress gradients and possibly the presence of defects. In addition, based on the in-situ TEM observations, void growth seems to occur through grain boundary and/or interfacial diffusion. However, in-situ STEM observations of fully opened voids post-failure show pileup of material at the Cu grain surfaces. This means that surface or interface diffusion is also very active during void growth in the presence of thermal stresses.

The demand for higher bandwidth and higher speed driven by semiconductor technology development draws a great deal of research efforts devoted to the development of high speed data communication. Challenges on electrical copper interconnects at high frequency make optical interconnect technologies become a promising alternative to conventional electrical interconnects at different levels. This doctoral dissertation describes polymer based nano- and micro-photonic devices for three-dimensional optical interconnects. Two areas are focused, (1) polymer based two-dimensional (2D) and three-dimensional (3D) photonic crystal fabrication and simulation for laser beam steering applications, (2) polymer based optical waveguide array and shared bus waveguide with embedded 45° micro-mirrors for board level optical interconnects. A three-dimensional (3D) face-centered cubic (FCC) type polymer based photonic crystal using the polymer material SU-8 was simulated and successfully fabricated using a polygonal prism based holographic fabrication method. The theoretical study of polymer based photonic crystals was carried out for laser beam steering, which is based on the superprism effect. Horizontally stacked two-dimensional (2D) photonic crystal was fabricated by a double exposure holographic interference method. The k-vector superprism effect, the principle for beam steering, was studied in detail through EFC (Equi-frequency Contour) analysis. A polymer based optical waveguide array with embedded 45° micro-mirrors for board level optical interconnects was prepared using a Ni metal hard mold by a UV imprint technique. A nickel based metal mold with 45º tilted surfaces on both ends of the channel waveguide was prepared through the electroplating process. To obtain a precise 45º tilted angle, a 50µm thick SU-8 layer was exposed under de-ionized water. High speed optical testing (10Gb/s) was carried out on the polymeric optical waveguide array with embedded 45º micro-mirrors on flexible substrate for out-of-plane optical interconnects. A polymer based 3-to-3 shared optical bus waveguide with opposite 45º micro-mirrors was designed and fabricated using the metallic hard mold method. The Ni metal hard mold was successfully prepared using the Ni electroplating method. This metallic hard mold provides a convenient way to fabricate the polymeric optical bus waveguide devices through the imprint technique. / text

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Parallel optical interconnects (POI) have attracted a great deal of attention in the past two decades as the system bandwidth continues to increase. Optical interconnects are known to have more advantages than their electrical counterparts in many aspects such as crosstalk, bandwidth distance product, power consumption, and RC time delay. The parallelization of several optical links is also an effective method to increase the aggregate data rate while keeping the component count manageable and to reduce the unit cost of optics, electronics, and packaging at lower line rate. / Parallel optical transceiver modules running at several gigabits per second are commercially available nowadays. Parallel optical receivers are one of the key components of parallel interconnected systems. In this work, we describe how a low-power parallel CMOS preamplifier IC and a deskew IC have been designed and fabricated through the IBM 0.13mum CMOS technology. The performances of three different transimpedance amplifier (TIA) topologies are compared experimentally. The best of the three TIAs shows a differential gain of 56.2dBO, 2.6GHz bandwidth, and less than -16dBm sensitivity with a bit-error-rate (BER) less than 10-12. The TIA consumes 2.5mW of power from a 1.2V supply while the channel power is 22mW with a 400mV pp differential output swing. / A novel method of accurately measuring the crosstalk power penalty with an on-chip PRBS generator is proposed and its implementation is described. The use of an on-chip PRBS generator to drive the dummy channels eliminates the data pattern dependence between the aggressors and the victim. The inevitable channel skew associated with parallel channels can be removed by a phase-locked loop (PLL) based deskew method. We investigated the skew compensation range of this method theoretically and our experimental results confirm our conclusion. / Various practical design and test techniques such as photodiode modeling, AC coupling, low-pass filtering and continuous skew generation, and their implementations, are discussed and implemented in this thesis.

With the industry striving for smaller devices, new technologies are developed to further miniaturize electronics devices. To this end, realization of 3D/non-planar interconnects, which aim at miniaturizing the interconnects formed between components on the same device, has attracted many researchers. This thesis focuses on a feasibility analysis for developing non-planar interconnects on various flexible substrates using laser assisted maskless microdeposition (LAMM), which is a pressure-less process. There are two types of flexible substrates that are used: double-sided copper substrates separated by a layer of polyethylene terephthalate (PET) as well as a polyethylene terephthalate flexible substrate with surface-mounted resistors. For both substrates, multiple types of experiments were conducted to discover procedures which result in the highest rate of success for forming conductive interconnects. Optimal process parameters and deposition techniques were determined after multiple experiments. After experiments were completed, the resultant substrates were subject to various characterization methodologies including optical and scanning electron microscopy, energy-dispersive X-ray spectroscopy, X-ray diffraction and profilometery. The results of these methodologies are documented in this thesis. After many types of experiments involving substrate manipulation of the double-sided copper substrates, it was shown that the silver nano-particles were more likely to form a conductive interconnect when a polished slant was fabricated on the substrate. Many deposition patterns were used for the flexible substrates with surface-mounted resistors. Of these patterns, the two patterns, the ‘zigzag’ and ‘dot solder’ patterns, proved to have a much higher success rate for creating conductive interconnects compared to the other patterns. During this study, the results of the experiments using the LAMM process show that this technology has great potential for creating non-planar interconnects on flexible substrates. The experiments however suggest that the process is very sensitive to the material composition and process parameters. As such, with a small change in parameters, the 3D interconnects can fail to be produced. It was also observed that the possibility of silver interconnect fractures is higher where dissimilar materials with different thermal expansion rates are used for the underlying substrates.

Differential interconnects are extensively used in high-speed digital circuits at fast data rates and in environments of high noise like backplanes. For such applications they are preferred over single-ended lines owing to their ability to reject common-mode noise. Differential schemes like Low Voltage Differential Signaling (LVDS) are used for wireless base stations and ATM switches in telecommunication applications, flat panel displays and servers and for system-level clock distribution. LVDS applications use data rates from 100 Mbps to about 1.5 Gbps and are expected to be highly immune to noise. However, noise will also be injected into differential signals at these high data rates, if there are irregularities in the interconnect setup. These anomalies may be via transitions from differential lines through power planes in power distribution systems, via stubs, asymmetric lengths of differential lines, different transition points for each of the differential vias etc. The differential setup is expected to be immune to such imbalances; however, investigation of these discontinuities indicate that sufficient signal energy can be leaked to power distribution networks (PDN) of packages and boards. The effect of this energy loss was examined in time-domain and was found to cause signal integrity effects like jitter. Irregular differential structures were compared with the equivalent single-ended configuration and symmetrical perfect differential lines. This thesis work quantifies signal to power coupling caused by irregular differential structures in the presence of PDN planes in frequency domain. Presence of noise in differential signaling is verified through a set of test vehicles. The jitter induced as a result of signal to power coupling from differential lines was also investigated.