A wireless sensor network (WSN) consists of a large number of networked sensor nodes deployed to sense and report a particular phenomenon to a base station. Currently, most WSNs use radio frequency (RF) communications, and this accounts for a significant amount of energy expended. Free space optical (FSO) communications using modulating retroreflectors is potentially attractive for WSNs, due to the lower communications energy required. However, for FSO communications, line of sight (LOS) is required between the transmitter and the receiver. In this thesis, a hybrid Radio Frequency/Free Space Optical (RF/FSO) WSN is proposed. FSO links are used for communications, with RF links providing backup in the absence of LOS. This network has the potential to lower the overall energy consumption of a traditional RF-only WSN. Chapter 1 introduces the WSN and outlines the motivation for the RF/FSO WSN. Chapters 2 and 3 describe the RF and FSO link models used for the RF/FSO WSN. Chapter 4 describes how the WSN networks are configured. The energy model for the sensor node is discussed in Chapter 5. Chapter 6 discusses how network traffic and energy consumption are modelled. The results of the RF/FSO WSN simulations are presented in Chapter 7. Chapter 8 discusses the conclusions from the thesis and suggests areas for future work. Simulations show that for the wide range of scenarios considered, the RF/FSO WSN consumes less energy and has a lifetime at least twice as long as the RF-only WSN. For low and average optical blocking conditions, the RF/FSO WSN is also able to offer at least the same level of network coverage as the RF-only WSN.

The work presented in this thesis fits within the broader area of fiber optics communications. This is an important area of research as it provides a breeding ground for the present and future technologies supporting the Internet. Due to the ever-increasing bandwidth demands worldwide, the network infrastructures that make up the Internet are continuously being upgraded. This thesis aims to identify key segments of the Internet that are deemed to become the Internet's bottleneck if new technology does not replace the current one. These are datacenter intra and inter-connects, and metropolitan core area networks. In each category, we provide a comprehensive overview of the state of the art, identify key impairments affecting data transmission, and suggest solutions to overcome them.   For datacenter intra and inter-connects, the key impairments are lack of bandwidth from electro-optic devices, and dispersion. Solutions attempting to tackle these impairments must be constrained by cost and power consumption. The provided solution is MultiCAP, an alternative advanced modulation format that is more tolerable to dispersion and provides bandwidth management features, while being flexible enough to sacrifice performance in order to gain simplicity. MultiCAP was the first advanced modulation format to achieve over 100~Gb/s in 2013 for a data-center interconnect and set the world record on data transmission over a single VCSEL in 2014 for a short reach data link.    On metro-core networks, the challenge is to efficiently mitigate carrier induced frequency noise generated by modern semiconductor lasers. We point out that, when such lasers are employed, the commonly used laser linewidth fails to estimate system performance, and we propose an alternative figure of merit we name "Effective Linewidth". We derive this figure of merit analytically, explore it by numerical simulations and experimentally validate our results by transmitting a 28~Gbaud DP-16QAM over an optical link. / <p>QC 20170602</p> / GRIFFON

Datacenter networks are not only larger but with new applications increasing the east-west traffic and the introduction of the spine leaf architecture there is an urgent need for high bandwidth, low cost, energy efficient interconnects. This paper will discuss the role integrated photonics can have in achieving datacenter requirements. We will review the state of the art and then focus on advances in optical switch fabrics and systems. The optical switch is of particular interest from the integration point of view. Current MEMS and LCOS commercial solutions are relatively large with relatively slow reconfiguration times limiting their use in packet based datacenter networks. This has driven the research and development of more highly integrated silicon photonic switch fabrics, including micro ring, Mach-Zehnder and MEMS device designs each with its own energy, bandwidth and scalability, challenges and trade-offs. Micro rings show promise for their small footprint, however they require an energy efficient means to maintain wavelength and thermal control. Latency requirements have been traditionally less stringent in datacenter networks compared to high performance computing applications, however with the increasing numbers of servers communicating within applications and the growing size of the warehouse datacenter, latency is becoming more critical. Although the transparent optical switch fabric itself has a minimal additional latency, we must also take account of any additional latency of the optically switched architecture. Proposed optically switched architectures will be reviewed.

Tan Xuesong. / "June 2004." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (p. 247-251). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

For the congestion issue, we found that the existing congestion models will very often over-estimate the congestion at the densely routed regions because real routers will perform rip-up and re-route operations and route the nets with detour to avoid overflow. We propose a 3-step approach that is designed to tackle this problem. It can simulate the global routing, detailed routing and rip-up and re-route process in the real routing procedure. Results show that the prediction accuracy can be improved by 30%. In addition, we have also implemented a routability-driven floorplanner with our congestion model. Results show that the number of un-routable wires can be reduced if the number of overflow tiles can be reduced during floorplanning. Then we studied and developed two post-processing steps to be applied on an interconnect optimized floorplan or placement to further reduce the total wirelength or area. For the wirelength issue, we presented an elegant solution to the cell flipping problem. We presented a detailed study of this cell flipping problem in a placement result to reduce interconnect length. We find the optimal flipping of the cells by formulating the cell flipping problem as a mixed integer linear programming problem to give the shortest total wirelength. In order to reduce the runtime, we proposed a cell orientation fixing step to fix the orientations of some cells. Results show that we can obtain optimal result by solving the mixed integer linear programming problem of the remaining variables directly or the problem can be solved by linear programming such that we can still obtain a result very close to the optimal solution with a much shorter runtime. For area reduction on an interconnect optimized floorplan, we proposed a new approach called deadspace utilization to reduce the total area of an interconnect optimized floorplan by making use of the shape flexibility of some modules. Results show that we can apply this deadspace utilization technique to reduce the area and wirelength of the original floorplan further, subject to the constraint of maintaining the routability and congestion of the original floorplan. / We have studied several interconnect-related optimization problems in floor-planning and placement of VLSI circuits in details. When the number of small logic gates is large in a circuit design, good netlist designs may still result in poor layouts because of various interconnect problems. Most of the problems cannot be fixed manually today because of the incomprehensible circuit complexity. Design automation techniques on interconnect issues in physical design of VLSI circuits becomes indispensable. Recently, congestion minimization and wirelength optimization are two hot topics in interconnect planning. / Sham Chiu Wing. / "March 2006." / Adviser: Young Fung Yu. / Source: Dissertation Abstracts International, Volume: 67-11, Section: B, page: 6634. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (p. 106-115). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Lai Tsz Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 123-129). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Cycle --- p.2 / Chapter 1.2 --- Physical Design Cycle --- p.4 / Chapter 1.3 --- Floorplanning --- p.7 / Chapter 1.3.1 --- Types of Floorplan and Floorplan Representations --- p.11 / Chapter 1.3.2 --- Interconnect-driven Floorplanning --- p.13 / Chapter 1.4 --- Motivations and Contributions --- p.17 / Chapter 1.5 --- Organization of this Thesis --- p.18 / Chapter 2 --- Literature Review on Floorplan Representation --- p.20 / Chapter 2.1 --- Slicing Floorplan Representation --- p.20 / Chapter 2.1.1 --- Normalized Polish Expression --- p.20 / Chapter 2.2 --- Non-slicing Floorplan Representations --- p.21 / Chapter 2.2.1 --- Sequence Pair (SP) --- p.21 / Chapter 2.2.2 --- Bounded-sliceline Grid (BSG) --- p.23 / Chapter 2.2.3 --- O-tree --- p.25 / Chapter 2.2.4 --- B*-tree --- p.26 / Chapter 2.3 --- Mosaic Floorplan Representations --- p.28 / Chapter 2.3.1 --- Corner Block List (CBL) --- p.28 / Chapter 2.3.2 --- Twin Binary Trees (TBT) --- p.31 / Chapter 2.3.3 --- Twin Binary Sequences (TBS) --- p.32 / Chapter 2.4 --- Summary --- p.34 / Chapter 3 --- Literature Review on Interconnect Optimization in Floorplan- ning --- p.37 / Chapter 3.1 --- Wirelength Estimation --- p.37 / Chapter 3.2 --- Congestion Optimization --- p.38 / Chapter 3.2.1 --- Integrated Floorplanning and Interconnect Planning --- p.41 / Chapter 3.2.2 --- Multi-layer Global Wiring Planning (GWP) --- p.43 / Chapter 3.2.3 --- Estimating Routing Congestion using Probabilistic Anal- ysis --- p.44 / Chapter 3.2.4 --- Congestion Minimization During Placement --- p.46 / Chapter 3.2.5 --- Modelling and Minimization of Routing Congestion --- p.48 / Chapter 3.3 --- Buffer Planning --- p.49 / Chapter 3.3.1 --- Buffer Clustering with Feasible Region --- p.51 / Chapter 3.3.2 --- Routability-driven Repeater Clustering Algorithm with Iterative Deletion --- p.55 / Chapter 3.3.3 --- Planning Buffer Locations by Network Flow --- p.58 / Chapter 3.3.4 --- Buffer Planning using Integer Multicommodity Flow --- p.60 / Chapter 3.3.5 --- Buffer Planning Problem using Tile Graph --- p.60 / Chapter 3.3.6 --- Probabilistic Analysis for Buffer Block Planning --- p.62 / Chapter 3.3.7 --- Fast Buffer Planning and Congestion Optimization --- p.63 / Chapter 3.4 --- Summary --- p.66 / Chapter 4 --- Congestion Evaluation: Wire Density Model --- p.68 / Chapter 4.1 --- Introduction --- p.68 / Chapter 4.2 --- Overview of Our Floorplanner --- p.70 / Chapter 4.3 --- Wire Density Model --- p.71 / Chapter 4.3.1 --- Computation of Ni --- p.72 / Chapter 4.3.2 --- Computation of Pi --- p.74 / Chapter 4.3.3 --- Usage of Mirror TBT --- p.76 / Chapter 4.4 --- Implementation --- p.76 / Chapter 4.4.1 --- Efficient Calculation of Ni --- p.76 / Chapter 4.4.2 --- Solving the LCA Problem Efficiently --- p.81 / Chapter 4.4.3 --- Cost Function --- p.81 / Chapter 4.4.4 --- Complexity --- p.81 / Chapter 4.5 --- Experimental Results --- p.82 / Chapter 4.6 --- Conclusion --- p.83 / Chapter 5 --- Buffer Planning: Simple Buffer Planning Method --- p.85 / Chapter 5.1 --- Introduction --- p.85 / Chapter 5.2 --- Variable Interval Buffer Insertion Constraint --- p.87 / Chapter 5.3 --- Overview of Our Floorplanner --- p.88 / Chapter 5.4 --- Buffer Planning --- p.89 / Chapter 5.4.1 --- Feasible Grids --- p.89 / Chapter 5.4.2 --- Table Look-up Approach --- p.89 / Chapter 5.5 --- Implementation --- p.91 / Chapter 5.5.1 --- Building the Look-up Tables --- p.91 / Chapter 5.5.2 --- An Example of Look-up Table Construction --- p.94 / Chapter 5.5.3 --- A Faster Approach for Building the Look-up Tables --- p.101 / Chapter 5.5.4 --- An Example of the Faster Look-up Table Construction --- p.105 / Chapter 5.5.5 --- I/O Pin Locations --- p.106 / Chapter 5.5.6 --- Cost Function --- p.110 / Chapter 5.5.7 --- Complexity --- p.111 / Chapter 5.6 --- Experimental Results --- p.112 / Chapter 5.6.1 --- Selected Value for A --- p.112 / Chapter 5.6.2 --- Performance of Our Floorplanner --- p.113 / Chapter 5.7 --- Conclusion --- p.116 / Chapter 6 --- Conclusion --- p.118 / Chapter A --- An Efficient Algorithm for the Least Common Ancestor Prob- lem --- p.120 / Bibliography --- p.123

Ma, Tilen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 98-100). / Abstracts in English and Chinese. / Abstract --- p.i / Chapter 0.1 --- Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Physical Design Cycle --- p.2 / Chapter 1.2 --- Floorplanning --- p.6 / Chapter 1.2.1 --- Floorplanning Objectives --- p.7 / Chapter 1.2.2 --- Common Approaches --- p.8 / Chapter 1.3 --- Motivations and Contributions --- p.11 / Chapter 1.4 --- Organization of the Thesis --- p.13 / Chapter 2 --- Literature Review on Placement Constraints in Floorplanning --- p.15 / Chapter 2.1 --- Introduction --- p.15 / Chapter 2.2 --- Algorithms for Abutment Constraint --- p.16 / Chapter 2.3 --- Algorithms for Alignment Constraint --- p.18 / Chapter 2.4 --- Algorithms for Boundary Constraint --- p.20 / Chapter 2.5 --- Unified Approach for Placement Constraints --- p.23 / Chapter 2.5.1 --- Representation of Placement Constraints --- p.23 / Chapter 2.5.2 --- Handling Relative Placement Constraints --- p.24 / Chapter 2.5.3 --- Examples for Handling Placement Constraints --- p.25 / Chapter 3 --- Literature Review on Bus-Driven Floorplanning --- p.28 / Chapter 3.1 --- Introduction --- p.28 / Chapter 3.2 --- Previous Work --- p.28 / Chapter 3.2.1 --- Zero-Bend Bus-Driven Floorplanning [3] --- p.28 / Chapter 3.2.2 --- Two-Bend Bus-Driven Floorplanning [1] --- p.32 / Chapter 4 --- Placement Constraints for Multi-Bend Bus in TCGs --- p.38 / Chapter 4.1 --- Introduction --- p.38 / Chapter 4.2 --- Transitive Closure Graph [6] --- p.39 / Chapter 4.3 --- Placement Constraints for Zero-Bend Bus --- p.41 / Chapter 4.4 --- Placement Constraints for Multi-Bend Bus --- p.44 / Chapter 4.5 --- Placement Constraints for Bus Ordering --- p.45 / Chapter 4.5.1 --- Natural Bus Ordering in TCGs --- p.45 / Chapter 4.5.2 --- Explicit Bus Ordering in TCGs --- p.46 / Chapter 5 --- TCG-Based Bus-Driven Floorplanning --- p.48 / Chapter 5.1 --- Motivation --- p.48 / Chapter 5.2 --- Problem Formulation --- p.49 / Chapter 5.3 --- Methodology --- p.50 / Chapter 5.3.1 --- Construction of Reduced Graphs --- p.51 / Chapter 5.3.2 --- Construction of Common Graph --- p.52 / Chapter 5.3.3 --- Spanning Tree for Bus Assignment --- p.53 / Chapter 5.3.4 --- Formation of Bus Components --- p.55 / Chapter 5.3.5 --- Bus Feasibility Check --- p.56 / Chapter 5.3.6 --- Overlap Removal --- p.57 / Chapter 5.3.7 --- Floorplan Realization --- p.58 / Chapter 5.3.8 --- Simulated Annealing --- p.58 / Chapter 5.3.9 --- Soft Module Adjustment --- p.60 / Chapter 5.4 --- Experimental Results --- p.60 / Chapter 5.5 --- Summary --- p.65 / Chapter 6 --- Conclusion --- p.67 / Chapter A --- Appendix --- p.69 / Chapter A.1 --- Well-Known Algorithms --- p.69 / Chapter A.1.1 --- Kruskal's Algorithm --- p.69 / Chapter A.1.2 --- Bellman-Ford Algorithm --- p.69 / Chapter A.2 --- Figures of Resulting Floorplans --- p.71 / Chapter A.2.1 --- Data Set One --- p.71 / Chapter A.2.2 --- Data Set Two --- p.80 / Chapter A.2.3 --- Data Set Three --- p.85 / Chapter A.2.4 --- Data Set Four --- p.92 / Bibliography --- p.98

Three dimensional (3-D) integrated circuits can be fabricated by bonding previously processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnects test structures were created by thermocompression bonding and the bond toughness was measured using the four-point test. The effects of bonding temperature, physical bonding and failure mechanisms were investigated. The surface effects on copper surface due to pre-bond clean (with glacial acetic acid) were also looked into. A maximum average bond toughness of approximately 35 J/m² was obtained bonding temperature 300 C. / Singapore-MIT Alliance (SMA)

With the industry striving for smaller devices, new technologies are developed to further miniaturize electronics devices. To this end, realization of 3D/non-planar interconnects, which aim at miniaturizing the interconnects formed between components on the same device, has attracted many researchers. This thesis focuses on a feasibility analysis for developing non-planar interconnects on various flexible substrates using laser assisted maskless microdeposition (LAMM), which is a pressure-less process. There are two types of flexible substrates that are used: double-sided copper substrates separated by a layer of polyethylene terephthalate (PET) as well as a polyethylene terephthalate flexible substrate with surface-mounted resistors. For both substrates, multiple types of experiments were conducted to discover procedures which result in the highest rate of success for forming conductive interconnects. Optimal process parameters and deposition techniques were determined after multiple experiments. After experiments were completed, the resultant substrates were subject to various characterization methodologies including optical and scanning electron microscopy, energy-dispersive X-ray spectroscopy, X-ray diffraction and profilometery. The results of these methodologies are documented in this thesis. After many types of experiments involving substrate manipulation of the double-sided copper substrates, it was shown that the silver nano-particles were more likely to form a conductive interconnect when a polished slant was fabricated on the substrate. Many deposition patterns were used for the flexible substrates with surface-mounted resistors. Of these patterns, the two patterns, the ‘zigzag’ and ‘dot solder’ patterns, proved to have a much higher success rate for creating conductive interconnects compared to the other patterns. During this study, the results of the experiments using the LAMM process show that this technology has great potential for creating non-planar interconnects on flexible substrates. The experiments however suggest that the process is very sensitive to the material composition and process parameters. As such, with a small change in parameters, the 3D interconnects can fail to be produced. It was also observed that the possibility of silver interconnect fractures is higher where dissimilar materials with different thermal expansion rates are used for the underlying substrates.

Dramatic advances are taking place in the microelectronic industry. The feature size continues to scale down and it is expected that the minimum feature size on the integrated circuit is expected to reach 9 nm by 2016, and there will be more than 8 billion transistors on a 310 cm² chip, according to various available roadmaps. Subsequently, this reduction in feature size would require the first-level input-output interconnects to decrease in pitch size to meet the increased number of transistors on the chip. Also, to minimize the on-chip interconnect delay, development of low-K dielectric/copper will become increasingly common in future devices. However, due to the low fracture strength of low-K dielectric, it is essential that the first-level interconnects exert minimal force on the die pads and therefore, do not crack or delaminate the low-K dielectric material. It is also preferable to have a wafer-level packaging approach to facilitate test-and-burn in and to produce known-good dies. Based on these growing demands from the microelectronics industry, there is a compelling need to develop innovative interconnect technologies. This thesis aims to develop one such innovative interconnect — G-Helix interconnect. G-Helix is a scalable lithography-based wafer-level electroplated compliant interconnect that has the potential to meet the fine-pitch first-level chip-to-substrate interconnect requirements. The three-mask fabrication of G-Helix is based on lithography, electroplating and molding (LIGA-like) technologies, and this fabrication can be easily integrated into large-area wafer-level fine-pitch batch processing. In this work, the fabrication, assembly, experimental reliability testing, and numerical physics-based modeling of the G-Helix interconnects will be presented. The fabrication of the interconnects will be demonstrated at 100μm pitch on a 20 x 20 mm die in a class 10/1000 cleanroom facility. The wafers with compliant interconnects will be singulated into individual dies and assembled on substrates using Pb/Sn eutectic solder. The assembly will then be subjected to air-to-air thermal cycling between 0℃and 100℃ and the reliability of the compliant interconnect will be assessed. In addition to the thermo-mechanical reliability testing, some of the dies with free-standing interconnects will also be used for measuring the compliance of the interconnects by compressing with a nanoindenter. In parallel to the experimental research, a numerical analysis study will also be carried out. The numerical model will use direction-, temperature, time-dependent, and time independent material constitutive properties as appropriate. The thermo-mechanical fatigue life of the compliant interconnect assembly will be determined and compared with the experimental data. Recommendations will be developed for further enhancement of reliability and reduction in pitch size.