Optical communication is distinguished for its enormous interconnect capacity over long distance. As the cost of optical components drops, high bandwidth optical systems were successfully employed into local area network and computer racks because electrical counterparts are not able to deal with the data rate demands for these applications. With the popularity of multi-core CPU in High Performance Computers, the board-to-board interconnects exclusive based on electrical technology in backplane applications become insufficient because of not only bandwidth crises, but also wiring congestions. Many researches have projected that the progress of optical technology will further push down the boundary demarcating electrical and optical domains in the interconnect hierarchy. Accordingly, backplane or even board-to-board level interconnects will benefit from the complement of optical interconnect. From architecture point of view, an optical bus implementation of the optical interconnect has the potential advantage of both huge bandwidth and elimination of wiring congestion. In contrast, optical waveguide and free-space interconnects although provide high bandwidth capacity, are essentially point-to-point technology which requires routing to a central switch on the backplane. The centralized approach that was based on substrate guided optical interconnects is the only way known that fulfills a uniform fan-out for different nodes in a bus architecture, which allows medium sharing among nodes. In this dissertation, innovative bit-interleaved optical backplane bus architecture is created based on centralized substrate-guide optical interconnect, which allows the tremendous bandwidth capacity to be shared by retaining the share bus architecture. Therefore, a secure and reliable high speed transmission channel could be established by distributing copies of confidential information separately. The feature provided by this innovative design cannot be fulfilled using electrical interconnects or other optical point-to-point technology without causing wiring congestions. In this dissertation, the optical characteristics of the centralized optical bus such as bandwidth and alignment tolerance are analyzed so that multi-channel implementation are successful on the fabricated optical interconnect layer. A 3-board-16-channel computer server using optical backplane board demonstrator using centralized optical bus was built upon the simulation, design and packaging work.

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A novel large-scale silicon system platform with 9.6cm² of active silicon interposer area is demonstrated. The platform contains three interposer tiles and two silicon bridges, and a novel self-alignment technology utilizing positive self-alignment structures (PSAS) and a novel mechanically flexible interconnect (MFI) technology are developed and used to align and interconnect tiles and bridges on an FR4 substrate. An accurate alignment < 8μm between silicon bridges and interposer tiles makes it possible to accommodate nanophotonics to enable a high bandwidth and low-energy system in the future. In addition, mechanically flexible interconnects and silicon bridges are used to provide electrical connections between interposer tiles without having to use motherboard-level interconnects. Finally, an elastomeric bump interposer is developed to enable the packaging of PSAS-enabled silicon systems, and PSAS' compatibility with a thermo-compression bonding process is demonstrated to enable a wide range of system configurations involving interposer tiles and bridges, including the multi-chip package configuration used with the elastomeric bump interposers.

It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2019, with the IC feature size shrinking to about 10nm, off-chip interconnects in an area array format will require a pitch of 95 µm. Also, as the industry adopts porous low-K dielectric materials, it is important to ensure that the stresses induced by the off-chip interconnects and the package do not crack or delaminate the low-K material. Compliant free-standing structures used as off-chip interconnects are a potential solution. However, there are several design, fabrication, assembly and integration research challenges and gaps with the current suite of compliant interconnects. Accordingly, as part of this research a unique parallel-path approach has been developed which enhances the mechanical compliance of the compliant interconnect without compromising the electrical parasitics. It also provides for redundancy and thus results in more reliable interconnects. Also, to meet both electrical and mechanical performance needs, as part of this research a variable compliance approach has been developed so that interconnects near the center of the die have lower electrical parasitics while the interconnects near the corner of the die have higher mechanical compliance. Furthermore, this work has developed a fabrication process which will facilitate cost-effective fabrication of free-standing compliant interconnects and investigated key factors which impact assembly yield of free-standing compliant interconnects. Ultimately the proposed approaches are demonstrated by developing an innovative compliant interconnect called FlexConnects. Hence, through this research it is expected that the developed compliant interconnect would address the needs of first level interconnects over the next decade and eliminate a bottleneck that threatens to impede the exponential growth in microprocessor performance. Also, the concepts developed in this research are generic in nature and can be extended to other aspects of electronic packaging.

Thesis (Ph.D.). / Written for the Dept. of Electrical and Computer Engineering. Title from title page of PDF (viewed 2008/07/23). Includes bibliographical references.