Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--Washington State University, August 2007. / Includes bibliographical references (p. 89-97).

In this work, copper bimetallic corrosion and inhibition in ultra large scale interconnect fabrication process is explored. Corrosion behavior of physical vapor deposited (PVD) copper on ruthenium on acidic and alkaline solutions was investigated with and without organic inhibitors. Bimetallic corrosion screening experiments were carried out to determine the corrosion rate. Potentiodynamic polarization experiments yielded information on the galvanic couples and also corrosion rates. XPS and FTIR surface analysis gave important information pertaining inhibition mechanism of organic inhibitors. Interestingly copper in contact with ruthenium in cleaning solution led to increased corrosion rate compared to copper in contact with tantalum. On the other hand when cobalt was in contact with copper, cobalt corroded and copper did not. We ascribe this phenomenon to the difference in the standard reduction potentials of the two metals in contact and in such a case a less noble metal will be corroded. The effects of plasma etch gases such as CF4, CF4+O2, C4F8, CH2F2 and SF6 on copper bimetallic corrosion was investigated too in alkaline solution. It was revealed that the type of etching gas plasma chemistry used in Cu interconnect manufacturing process creates copper surface modification which affects corrosion behavior in alkaline solution. The learning from copper bimetallic corrosion studies will be useful in the development of etch and clean formulations that will results in minimum defects and therefore increase the yield and reliability of copper interconnects.

abstract: Flexible conducting materials have been in the forefront of a rapidly transforming electronics industry, focusing on wearable devices for a variety of applications in recent times. Over the past few decades, bulky, rigid devices have been replaced with a surging demand for thin, flexible, light weight, ultra-portable yet high performance electronics. The interconnects available in the market today only satisfy a few of the desirable characteristics, making it necessary to compromise one feature over another. In this thesis, a method to prepare a thin, flexible, and stretchable inter-connect is presented with improved conductivity compared to previous achievements. It satisfies most mechanical and electrical conditions desired in the wearable electronics industry. The conducting composite, prepared with the widely available, low cost silicon-based organic polymer - polydimethylsiloxane (PDMS) and silver (Ag), is sandwiched between two cured PDMS layers. These protective layers improve the mechanical stability of the inter-connect. The structure can be stretched up to 120% of its original length which can further be enhanced to over 250% by cutting it into a serpentine shape without compromising its electrical stability. The inter-connect, around 500 µm thick, can be integrated into thin electronic packaging. The synthesis process of the composite material, along with its electrical and mechanical and properties are presented in detail. Testing methods and results for mechanical and electrical stability are also illustrated over extensive flexing and stretching cycles. The materials put into test, along with conductive silver (Ag) - polydimethylsiloxane (PDMS) composite in a sandwich structure, are copper foils, copper coated polyimide (PI) and aluminum (Al) coated polyethylene terephthalate (PET). / Dissertation/Thesis / Masters Thesis Electrical Engineering 2020

In search of higher speed and integration, the integrated circuit (IC) technology is scaling down. The total on-chip interconnect length is increasing exponentially. In fact, interconnect takes up the most part of the total chip area. The parasitics associated with these interconnect have significant impact on the circuit performance. Some of the effects of parasitics include cross talk, voltage drop and high current density. These issues can result in cross-talk induced functional failure and failures due to IR drop and electro-migration. This has resulted in interconnect- driven design trend in state-of-the-art integrated circuits. Reliability analysis, that includes simulating the effects of parasitics for voltage drop, current density, has become one of the most important steps in the VLSI design flow. Most of the CAD/EDA tools available, map these analysis results two dimensionally. Al- though this helps the designer, providing a three dimensional view of these results is highly desirable when dealing with complex circuits. In pursuit of visualizing reliability analysis results three dimensionally, as a first step, this work presents a tool that can visualize IC interconnect three di- mensionally. Throughout the course of this research open source tools were used to achieve the objective. In this work the circuit layout is stored as an OpenAc- cess database. A C++ program reads the design information using OpenAccess API and converts it to the .OBJ file format. Art of Illusion, an open source 3D modeling and rendering tool, reads this .OBJ file and models the IC interconnect three-dimensionally. In addition, Eclipse, an open source java IDE is used as a development platform. The tool presented has the capability to zoom in, zoom out and pan in real time.

No description available.

Global interconnect reliability is becoming a bigger issue as we scale down further into the submicron regime. As transistor dimensions get smaller, variations in the manufacturing process, and temperature variations may cause undesired behavior, and as a result, compromise performance. This work makes an effort to characterize the effects of such variations, to provide designers with a guideline for making designs tolerant to these variations while benefiting from tighter design margins. Since interconnects contribute to most of the delay and power on a chip, interconnect performance becomes a primary issue in design. One of the main concerns when considering physical transistor dimension variations is the effect on delay. Due to smaller transistor dimensions, the photolithographic process may produce transistors with significant variations from the ideal physical dimensions. Such variations cause delay uncertainty which can lead to over or underestimation in the design phase. This work examines interconnects to establish a guideline of the effect that process variations have on delay. A repeated interconnect is analyzed and the effects of physical device variations on delay are observed. Given the delay distribution in the presence of Leff variation, a supply voltage assignment technique is proposed to correct the observed deviation from the nominal delay on a long, repeated interconnect. This technique results in a significant reduction of the delay distribution, with a negligible power overhead. After looking at static variation effects on interconnect performance, this thesis addresses thermal variations on global signals, which cause delay degradation and may lead to timing failures. Given the presence of a large thermal gradient along a clock signal in a data path clocked by two leaves of an H-tree, several thermal scenarios which can compromise timing are discussed. A buffer-based skew compensation technique is proposed to correct the effect of thermal and manufacturing variations on this system. Having characterized repeated interconnect performance under process variations, the bandwidth of the line can be more effectively utilized by using a technique called phase coding. Phase coded interconnects are introduced in the context of using them once an interconnect has been adequately modeled in the presence of variations. With guidelines quantifying the effects of process variations on interconnect techniques and careful characterization, designers can factor these considerations into their design process, reducing the variation from the nominal expected behavior and allowing for smaller design margins. This will lead to more reliable products as we advance into future technologies and transistor dimensions get smaller.

A computationally efficient, discrete model is presented for transmission line analysis and passive model order reduction of high-speed interconnect systems. The development of this model was motivated by the on-going efforts in chip/package co-design to route a major portion of the on-chip clock and high-speed data buses through the package in order to overcome the bandwidth reduction and delay caused by the high ohmic loss of on-chip wiring. The geometric complexity of the resulting interconnections is such that model order reduction is essential for rapid and accurate signal integrity assessment to support pre-layout design iteration and optimization. The modal network theory of the skin effect in conjunction with the theory of compact differences is used for the development of discrete models for dispersive, multi-conductor interconnects compatible with passive model order reduction algorithms. The passive reduced-order interconnect modeling algorithm, PRIMA, is then used on the resulting discrete model to generate a low-order, multi-port macromodel for interconnect networks. Numerical examples are used to demonstrate the validity and efficiency of the proposed model.

Major challenges in maintaining quality and reliability in today’s microelectronics devices come from the ever increasing level of integration in the device fabrication, as well as the high level of current densities that are carried through the microchip during operation. In order to have a framework for design and reliability assessment, it is imperative to develop a predictive capability for the thermal response of micro-electronic components. A computationally efficient and accurate multi-scale transient thermal methodology was developed using a combination of two different approaches: “Progressive Zoom-in” method and “Proper Orthogonal Decomposition (POD)” technique. The proposed technique has the capability of handling several decades of length scale from tens of millimeter at “package” level to several nanometers at “interconnects” level at a considerably lower computational cost, while maintaining satisfactory accuracy. This ability also applies for time scales from seconds to microseconds corresponding to various transient thermal events. The proposed method also provides the ability to rapidly predict thermal responses under different power input patterns, based on only a few representative detailed simulations, without compromising the desired spatial and temporal resolutions. It is demonstrated that utilizing the proposed model, the computational time is reduced by at least two orders of magnitude at every step of modeling. Additionally, a novel experimental platform was developed to evaluate rapid transient Joule heating in embedded nanoscale metallic films representing buried on-chip interconnects that are not directly accessible. Utilizing the state-of-the-art sub-micron embedded resistance thermometry the effect of rapid transient power input profiles with different amplitudes and frequencies were studied. It is also demonstrated that a spatial resolution of 6 µm and thermal time constant of below 1 µs can be achieved using this technique. Ultimately, the size effects on the thermal and material properties of embedded metallic films were studied. A state-of-the-art technique to extract thermal conductivity of embedded nanoscale interconnects was developed. The proposed structure is the first device that has enabled the conductivity measurement of embedded metallic films on a substrate. It accounts for the effect of the substrate and interface without compromising the sensitivity of the device to the thermal conductivity of the metallic film. Another advantage of the proposed technique is that it can be integrated within the structure and be used for measurements of embedded or buried structures such as nanoscale on chip interconnects, without requiring extensive micro-fabrication. The dependence of the thermal conductivity on temperature was also investigated. The experimentally measured values for thermal conductivity and its dependence on temperature agree well with previous studies on free-standing nanoscale metallic bridges.

No description available.