<p>The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz. </p><p>In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current </p><p>The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.</p>

In mobile communication new applications like wireless internet and mobile video have increased the demand of data-rates. Therefore, new more wideband systems are being implemented. Power amplifiers in the base-stations that simultaneously handle these wideband signals for many terminals (handhelds) need to be highly linear with a considerable band-width. In the past decade LDMOS has been the dominating technology for use in these RF-power amplifiers. In this work LDMOS transistors possible to fabricate in a normal CMOS process have been optimized and analyzed for RF-power applications. Their non-linear behavior has been explored using load-pull measurements. The mechanisms of the non-linear input capacitance have been analyzed using 2D TCAD simulations. The investigation shows that the input capacitance is a large contributor to phase distortion in the transistor. Computational load-pull TCAD methods have been developed for analysis of RF-power devices in high-efficiency operation. Methods have been developed for class-F with harmonic loading and for bias-modulation. Load-pull measurements with drain-bias modulation in a novel measurement setup have also been conducted. The investigation shows that the combination of computational load-pull of physical transistor structures and direct measurement evaluation with modified load-pull is a viable alternative for future design of RF-power devices. Simulations and measurements on the designed LDMOS shows a 10 to 15 % increase in drain efficiency in mid-power range both in simulations and measurements. The computational load-pull method has also been used to investigate the power capability of LDMOS transistors on SOI. This study indicates that either a low-resistivity or high-resistivity substrate should be used in manufacturing of RF-power LDMOS transistors on SOI to achieve optimum efficiency. Based on a proper substrate selection these devices exhibit a 10 % higher drain-efficiency mainly due to lower dissipated power in the devices.

Today, the silicon technology is well established for RF-applications (f~1-100 GHz), with emphasis on the lower frequencies (f &lt; 5 GHz). The field of RF power devices is extensive concerning materials and devices. One of the important RF-devices is the silicon LDMOS transistor. A large extent of the research presented in the thesis concerns studies of this device, which have resulted in increased understanding of the device behavior and improved performance. The thesis starts with a brief survey of the RF-field, including the LDMOS transistor, followed by a description of the methods used in the investigations; simulations, modeling and measurements. Specific results presented in the appended papers are also briefly summarized. A new concept for LDMOS transistors, which allows for both high frequency and high voltage operation, has been developed and characterized. World-record performance in terms of output power density was obtained: over 1 W/mm at 50 V and 3.2 GHz. Further understanding and improvements of the device are achieved using simulations and modeling. For determination of model parameters a new general parameter extraction technique was developed. The method has been successfully used for a large variety of high-frequency devices, and has been frequently used in the modeling work in this thesis. Important properties of RF-power devices are the device linearity and power efficiency. Extensive studies regarding the efficiency were conducted using numerical simulations and modeling of the off-state output resistance, which is correlated to the efficiency. The results show that significant improvements can be obtained for devices on both bulk- and SOI-substrates, using thin high-resistivity substrates and very low-resistivity SOI-substrates, respectively. Finally a new approach to drastically reduce substrate crosstalk by using very low-resistivity SOI substrate is proposed. Experimentally, a reduction of 20-40 dB was demonstrated in the GHz range compared to high-resistivity SOI substrate.

The emergence of new communication standards has put a key challenge for semiconductor industry to develop RF devices that can handle high power and high data rates simultaneously. The RF devices play a key role in the design of power amplifiers (PAs), which is considered as a heart of base-station. From economical point of view, a single wideband RF power module is more desirable rather than multiple narrowband PAs especially for multi-band and multi-mode operation. Therefore, device modeling has now become much more crucial for such applications. In order to reduce the device design cycle time, the researchers also heavily rely on computer aided design (CAD) tools. With improvement in CAD technology the model extraction has become more accurate and device physical structure optimization can be carried out with less number of iterations. LDMOS devices have been dominating in the communication field since last decade and are still widely used for PA design and development. This thesis deals with the optimization of RFLDMOS transistor and its evaluation in different PA classes, such as linear, switching, wideband and multi-band applications. For accurate evaluation of RF-LDMOS transistor parameters, some techniques are also developed in technology CAD (TCAD) using large signal time domain computational load-pull (CLP) methods. Initially the RF-LDMOS is studied in TCAD for the improved RF performance. The physical intrinsic structure of RF-LDMOS is provided by Infenion Technologies AG. A reduced surface field (RESURF) of low-doped drain (LDD) region is considered in detail because it plays an important role in RF-LDMOS devices to obtain high breakdown voltage (BVDS). But on the other hand, it also reduces the RF performance due to high on-resistance (Ron). The excess interface state charges at the RESURF region are introduced to reduce the Ron, which not only increases the dc drain current, but also improve the RF performance in terms of power, gain and efficiency. The important achievement is the enhancement in operating frequency up to 4 GHz. In LDD region, the effect of excess interface charges at the RESURF is also compared with dual implanted-layer of p-type and n-type. The comparison revealed that the former provides 43 % reduction in Ron with BVDS of 70 V, while the later provides 26 % reduction in Ron together with BVDS of 64 - 68 V. In the second part of my research work, computational load pull (CLP) simulation technique is used in TCAD to extract the impedances of RF-LDMOS at different frequencies under large signal operation. Flexible matching is an issue in the design of broadband or multi-band PAs. Optimum impedance of RF-LDMOS is extracted at operating frequencies of 1, 2 and 2.5 GHz in class AB PA. After this, CLP simulation technique is further developed in TCAD to study the non-linear behavior of RF devices. Through modified CLP technique, non-linear effects inside the transistor structure are studied by conventional two-tone RF signals in time domain. This is helpful to detect and understand the phenomena, which can be resolved to improve the device performance. The third order inter-modulation distortion (IMD3) of RF- LDMOS was observed at different power levels. The IMD3 of −22 dBc is obtained at 1-dB compression point (P1-dB), while at 10 dB back off the value increases to −36 dBc. These results were also verified experimentally by fabricating a linear PA. Similarly, CLP technique is developed further for the analysis of RF devices in high efficiency operation by investigating the odd harmonic effects for the design of class-F PA. RF-LDMOS can provide a power added efficiency (PAE) of 81.2 % in class-F PA at 1 GHz in TCAD simulations. The results are verified by design and fabrication of class-F PA using large signal model of the similar device in ADS. In fabrication, a PAE of 76 % is achieved.

The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz. In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.

In this thesis the models of Si-LDMOS transistors have been investigated with Agilent EEsof ADS version 2002a for operation in the 2-6 GHz frequency range. The first one is the Motorola’s (MRF21010) model based on a 30 mm prototype of a Si-LDMOS transistor. The second one is a model based on a 1 mm prototype of Si-LDMOS transistor developed at Chalmers University. Large-signal simulations of Chalmers’ model have demonstrated results, which lead to the conclusion that,this model cannot be efficiently utilised for design for a PA in the 2-6 GHz frequency range. However, additional simulations with reduced Rd (drain losses) show the deep impact of this parameter on the main properties of the designed PA. Hence, it is important to take it into account during new processes of Si-LDMOS as well as to improve the CAD model. The final conclusion regarding Si-LDMOS cannot be made just based on these simulation results, since they are not in accordance with the published ones. The next step should be aimed at improving the model and further investigation of Si-LDMOS to prove their ability to operate in the 2-6 GHz frequency range.

With increasing amount of user data and applications in wireless communication technology, demands are growing on performance and fabrication costs. One way to decrease cost is to integrate the building blocks in an RF system where digital blocks and high power amplifiers then are combined on one chip. This thesis presents LDMOS transistors integrated in a 65 nm CMOS process without adding extra process steps or masks. High power performance of the LDMOS is demonstrated for an integrated WLAN-PA design at 2.45 GHz with 32.8 dBm output power and measurements also showed that high output power is achievable at 5.8 GHz. For the first time, this kind of device is moreover demonstrated at X-band with over 300 mW/mm output power, targeting communication and radar systems at 8 GHz. As SOI is increasing in popularity due to better device performance and RF benefits, the buried oxide can cause thermal problems, especially for high power devices. To deal with self-heating effects and decrease the RF substrate losses further, this thesis presents a hybrid substrate consisting of silicon on top of polycrystalline silicon carbide (Si-on-poly-SiC). This hybrid substrate utilizes the high thermal conductivity of poly-SiC to reduce device self-heating and the semi-insulating properties to reduce RF losses. Hybrid substrates were successfully fabricated for the first time in 150 mm wafer size by wafer bonding and evaluation was performed in terms of both electrical and thermal measurements and compared to a SOI reference. Successful LDMOS transistors were fabricated for the first time on this type of hybrid substrate where no degradation in electrical performance was seen comparing the LDMOS to identical transistors on the SOI reference. Measurements on calibrated resistors showed that the thermal conductivity was 2.5 times better for the hybrid substrate compared to the SOI substrate. Moreover, RF performance of the hybrid substrate was investigated and the semi-insulating property of poly-SiC showed to be beneficial in achieving a high equivalent substrate parallel resistance and thereby low substrate losses. In a transistor this would be equal to better efficiency and output power. In terms of integration, the hybrid substrate also opens up the possibility of heterogeneous integration where silicon devices and GaN devices can be fabricated on the same chip.

Emerging wireless standards are designed to be spectrally efficient to address the high cost of licensing wireless spectra. Unfortunately, the resulting signals have a high peak-to-average ratio that reduces the base station power amplifier efficiency at the back-off power level. The wasted energy is converted to heat that degrades the device reliability and increases the base-station’s carbon footprint and cooling requirements. In addition, these new standards place stringent re- quirements on the amplifier output power, linearity, efficiency, and bandwidth. To improve the back-off efficiency, a Doherty amplifier, which uses two device in parallel for back-off efficiency enhancement, is deployed in a typical base station. Unfortunately, the conventional Doherty amplifier is narrowband and thus cannot satisfy the bandwidth requirement of the modern base station that needs to support multiple standards and backward compatibility. In this thesis, we begin by studying the class F/F−1 high efficiency mode of operation. To this end, we designed a narrowband, harmonically-tuned 3.3 GHz, 10 W GaN high efficiency amplifier. Next, we investigate how to simultaneously achieve high efficiency and broad bandwidth by harnessing the simplified real frequency technique for the broadband matching network design. A 2 to 3 GHz, 45 W GaN amplifier and a 650 to 1050 MHz, 45 W LDMOS amplifier were designed. Finally, we analyze the conventional Doherty amplifier to determine the cause of its narrow bandwidth. We find that the narrow bandwidth can be attributed to the band-limited quarter-wave transformer as well as the widely adopted traditional design technique. As an original contribution to knowledge, we propose a novel Doherty amplifier configuration with intrinsically broadband characteristics by analyzing the load modulation concept and the conventional Doherty amplifier. The proposed amplifier uses asymmetrical drain voltage biases and symmetrical devices and it does not require a complex mixed-signal setup. To demonstrate the proposed concept in practice, we designed a 700 to 1000 MHz, 90 W GaN broadband Doherty amplifier. Moreover, to show that the proposed concept is applicable to high power designs, we designed a 200 W GaN broadband Doherty amplifier in the same band. In addition, to show that the technique is independent of the device technology, we designed a 700 to 900 MHz, 60 W LDMOS broadband Doherty amplifier. Using digital pre-distortion, the three prototypes were shown to be highly linearizable when driven with wideband 20 MHz LTE and WCDMA modulated signals and achieved excellent back-off efficiency. Lastly, using the insights from the previous analyses, we propose a novel mixed-technology Doherty amplifier with an extended and reconfigurable back-off level as well as an improved power utilization factor. The reconfigurability of the proposed amplifier makes it possible to customize the back-off level to achieve the highest average efficiency for a given modulated signal without redesigning the matching networks. A 790 to 960 MHz, 180 W LDMOS/GaN Doherty amplifier demonstrated the extended bandwidth and reconfigurability of the back-off level. The proposed amplifier addresses the shortcomings of the conventional Doherty amplifier and satisfies the many requirements of a modern base station power amplifier.

Emerging wireless standards are designed to be spectrally efficient to address the high cost of licensing wireless spectra. Unfortunately, the resulting signals have a high peak-to-average ratio that reduces the base station power amplifier efficiency at the back-off power level. The wasted energy is converted to heat that degrades the device reliability and increases the base-station’s carbon footprint and cooling requirements. In addition, these new standards place stringent re- quirements on the amplifier output power, linearity, efficiency, and bandwidth. To improve the back-off efficiency, a Doherty amplifier, which uses two device in parallel for back-off efficiency enhancement, is deployed in a typical base station. Unfortunately, the conventional Doherty amplifier is narrowband and thus cannot satisfy the bandwidth requirement of the modern base station that needs to support multiple standards and backward compatibility. In this thesis, we begin by studying the class F/F−1 high efficiency mode of operation. To this end, we designed a narrowband, harmonically-tuned 3.3 GHz, 10 W GaN high efficiency amplifier. Next, we investigate how to simultaneously achieve high efficiency and broad bandwidth by harnessing the simplified real frequency technique for the broadband matching network design. A 2 to 3 GHz, 45 W GaN amplifier and a 650 to 1050 MHz, 45 W LDMOS amplifier were designed. Finally, we analyze the conventional Doherty amplifier to determine the cause of its narrow bandwidth. We find that the narrow bandwidth can be attributed to the band-limited quarter-wave transformer as well as the widely adopted traditional design technique. As an original contribution to knowledge, we propose a novel Doherty amplifier configuration with intrinsically broadband characteristics by analyzing the load modulation concept and the conventional Doherty amplifier. The proposed amplifier uses asymmetrical drain voltage biases and symmetrical devices and it does not require a complex mixed-signal setup. To demonstrate the proposed concept in practice, we designed a 700 to 1000 MHz, 90 W GaN broadband Doherty amplifier. Moreover, to show that the proposed concept is applicable to high power designs, we designed a 200 W GaN broadband Doherty amplifier in the same band. In addition, to show that the technique is independent of the device technology, we designed a 700 to 900 MHz, 60 W LDMOS broadband Doherty amplifier. Using digital pre-distortion, the three prototypes were shown to be highly linearizable when driven with wideband 20 MHz LTE and WCDMA modulated signals and achieved excellent back-off efficiency. Lastly, using the insights from the previous analyses, we propose a novel mixed-technology Doherty amplifier with an extended and reconfigurable back-off level as well as an improved power utilization factor. The reconfigurability of the proposed amplifier makes it possible to customize the back-off level to achieve the highest average efficiency for a given modulated signal without redesigning the matching networks. A 790 to 960 MHz, 180 W LDMOS/GaN Doherty amplifier demonstrated the extended bandwidth and reconfigurability of the back-off level. The proposed amplifier addresses the shortcomings of the conventional Doherty amplifier and satisfies the many requirements of a modern base station power amplifier.

This thesis discusses the design, construction and testing of a highefficiency, 100 MHz, 1 kW, Class-E solid state power amplifier. The design was performed with the aid of computer simulations using electronic design software (ADS). The amplifier was constructed around Ampleon's BLF188XR LDMOS transistor in a single ended design. The results for 100 MHz operation show a power added efficiency of 82% at 1200 W pulsed power output. For operation at 102 MHz results show a power added efficiency of 86% at 1050 W pulsed power output. Measurements of the drain- and gate voltage waveforms provide validation of Class-E operation.