Tato práce se zabývá popisem základních vlastností LDMOS tranzistorů. V první části práce jsou rozebrány vlastnosti LDMOS tranzistorů, jejich základní parametry a techniky pro vylepšení parametrů těchto tranzistorů. V další části je rozebrána spolehlivost LDMOS tranzistorů, tato část popisuje bezpečnou pracovní oblast (SOA), injekci horkých nosičů (HCI) a negativní teplotní stabilitu (NBTI). Poslední teoretická část popisuje používané modely pro simulaci ESD událostí. Praktická část práce je zaměřena na simulaci základních parametrů PLDMOS a NLDMOS tranzistorů, porovnání simulovaných a změřených koncentračních profilů. Dále se práce zabývá simulacemi změny geometrických parametrů PLDMOS tranzistoru a vliv těchto změn na elektrické parametry. Poslední část práce tvoří TLP simulace, které zkoumají elektrické vlastnosti PLDMOS tranzistoru při použití jako ESD ochrana.

Předkládaná práce se zabývá parametrem “Reverse Recovery Time“ u polovodičových prvků a jeho vlivem na typické spínací obvody. V první části práce je objasněno co je “Reverse Recovery Time“ a jeho jednotlivé části. V další sekci je popsána jeho fyzikální podstata. Na konci teoretická části je rozebrán jeho efekt na spínací ztráty a doporučená metoda měření tohto parametru . Praktická část práce je zaměřena na simulace Dpdr45nres45 v prostředích Cadence a TCAD. Poslední část se zabývá návrhem obvodu na měření u reálných diod a samotným měřením diod a tranzistorů.

Bidirectional power switching devices are needed in many power management applications, particularly in lithium-ion battery protection circuitry. A monolithic bidirectional power switch fabricated with a simplified CMOS technology is introduced in this dissertation. Throughout the design process, ISE TCAD tool plays an important role. Design variables are carefully analyzed to improve the device performance or yield the best trade off. Optimization is done with the help of TCAD simulation and theoretical calculations. The device has been successfully fabricated using simplified 0.5 micron CMOS process. The experimental result shows a breakdown voltage of 25V. Due to the interdigitated source to source design, the inter-terminal current flowing path is effectively reduced to a few microns. The experimental result shows an ultra low specific on resistance. In comparison with other bi-directional power semiconductor switches by some major semiconductor manufacturers, the proposed BDS device has less than one half of the specific on resistance, thus substantially lower on state power loss of the switch. The proposed BDS device has a unique NPNPN structure, in comparison with NPNP structure, which is the analytical structure for CMOS latch-up, the proposed device inherently exhibits a better latch up immunity than CMOS inverter, thanks to the negative feed back mechanism of the extra NPN parasitic BJT transistor. In order to implement the device into simulators like PSPICE or Cadence IC Design, a compact model named variable resistance model has been built. This simple analytical model fits quite well with experimental data, and can be easily implemented by Verilog-A or other hardware description languages. Also, macro modeling is possible provided that the model parameters can be extracted from experimental curves. Several advanced types of BDS devices have been proposed, they exceed the basic BDS design in terms of breakdown voltage and /or on resistance. These advanced structures may be prominent for further improvement of the basic BDS device to a higher extend. Some cell phone providers such as Nokia is already asking for higher breakdown voltage of BDS device, due to the possibility of incidentally insert the battery pack into the cell phone with wrong pin polarity. Hopefully, the basic BDS design or one of these advanced types may eventually be implemented into the leading brand cell phone battery packs.

One of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices the peak of the lateral field is lowered by reducing the doping concentration near the drain and by providing a smooth junction transition instead of an abrupt one. Therefore, the amount of hot carrier generation for a given supply voltage and the influence of a certain physical damage on the electrical characteristics is decreased dramatically. A complete understanding of the hot carrier degradation problem in sub-micron 0.25um LD MOSFETs is presented in this work. First we discuss the degradation mechanisms observed under, for circuit operation, somewhat artificial but well-controlled uniform-substrate hot electron and substrate hot-hole injection conditions. Then the more realistic case of static channel hot carrier degradation is treated, and some important process-related effects are illustrated, followed by the behavior under the most relevant case for real operation, namely dynamic degradation. An Accurate and practical parameter extraction is used to obtain the LD MOSFETs model parameters, with the experiment verification. Good agreement between the model simulation and experiment is achieved. The gate charge transfer performance is examined to demonstrate the hot carrier effect. Furthermore, In order to understand the dynamic stress on the LD MOSFET and its effect on RF circuit, the hot-carrier injection experiment in which dynamic stress with different duty cycle applied to a LD MOS transistor is presented. A Class-C power amplifier is used to as an example to demonstrate the effect of dynamic stress on RF circuit performance. Finally, the strategy for improving hot carrier reliability and a forecast of the hot carrier reliability problem for nano-technologies are discussed. The main contribution of this work is, it systemically research the hot carrier reliability issue on the sub-micron lateral doped drain MOSFETs, which is induced by static and dynamic voltage stress; The stress condition mimics the typical application scenarios of LD MOSFET. Model parameters extraction technique is introduced with the aid of the current device modeling tools, the performance degradation model can be easily implement into the existing computer-aided tools. Therefore, circuit performance degradation can be accurately estimated in the design stage. CMOS technologies are constantly scaled down. The production on 65 nm is on the market. With the reduction in geometries, the devices become more vulnerable to hot carrier injection (HCI). HCI reliability is a must for designs implemented with new processes. Reliability simulation needs to be implemented in PDK libraries located on the modeling stage. The use of professional tools is a prerequisite to develop accurate device models, from DC to GHz, including noise modeling and nonlinear HF effects, within a reasonable time. Designers need to learn to design for reliability and they should be educated on additional reliability analyses. The value is the reduction of failure and redesign costs.

In this work an n-channel In0.65Ga0.35As LDMOS with Al2O3 as gate dielectric is investigated. Instead of using traditional Si process for LDMOS, we suggest In0.65Ga0.35As as substitute material due to its higher electron mobility and its promising for power applications. The proposed 0.5-µm channel-length LDMOS cell is studied through device TCAD simulation tools. Due to different gate dielectric, comprehensive comparisons between In0.65Ga0.35As LDMOS and Si LDMOS are made in two ways, structure with the same cross-sectional dimension, and structure with different thickness of gate dielectric to achieve the same gate capacitance. The on-resistance of the new device shows a big improvement with no degradation on breakdown voltage over traditional device. Also it is indicated from these comparisons that the figure of merit(FOM) Ron·Qg of In0.65Ga0.35As LDMOS shows an average of 91.9% improvement to that of Si LDMOS. To further explore the benefit of using In0.65Ga0.35As LDMOS as switch in power applications, DC-DC buck converter is utilized to observe the performance of LDMOS in terms of power efficiency. The LDMOS performance is experimented with operation frequency of the circuit sweeping in the range from 100 KHz to 100 MHz. It turns out InGaAs LDMOS is good candidate for power applications.

Galactic-cosmic-rays (GCR) exist in space from unknown origins. A cosmic ray is a very high energy electron, proton, or heavy ion. As a GCR transverses a power semiconductor device, electron-hole-pairs (ehps) are generated along the ion track. Effects from this are referred to as single-event-effects (SEEs). A subset of a SEE is single-event burnout (SEB) which occurs when the parasitic bipolar junction transistor is triggered leading to thermal runaway. The failure mechanism is a complicated mix of photo-generated current, avalanche generated current, and activation of the inherent parasitic bipolar transistor. Current space-borne power systems lack the utility and advantages of terrestrial power systems. Vertical-double-diffused MOSFETs (VDMOS) is by far the most common power semiconductor device and are very susceptible to SEEs by their vertical structure. Modern space power switches typically require system designers to de-rate the power semiconductor switching device to account for this. Consequently, the power system suffers from increased size, cost, and decreased performance. Their switching speed is limited due to their vertical structure and cannot be used for MHz frequency applications limiting the use of modern digital electronics for space missions. Thus, the Power Semiconductor Research Laboratory at the University of Central Florida in conjunction with Sandia National Laboratories is developing a rad-hard by design lateral-double-diffused MOSFET (LDMOS). The study provides a novel in-depth physical analysis of the mechanisms that cause the LDMOS to burnout during an SEE and provides guidelines for making the LDMOS rad-hard to SEB. Total dose radiation, another important radiation effect, can cause threshold voltage shifts but is beyond the scope of this study. The devices presented have been fabricated with a known total dose radiation hard CMOS process. Single-event burnout data from simulations and experiments are presented in the study to prove the viability of using the LDMOS to replace the VDMOS for space power systems. The LDMOS is capable of higher switching speeds due to a reduced drain-gate feedback capacitance (Miller Capacitor). Since the device is lateral it is compatible with complimentary-metal-oxide-semiconductor (CMOS) processes, lowering developing time and fabrication costs. High switching frequencies permit the use of high density point-of-load conversion and provide a fast dynamic response.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005. / In RF power transistor characterisation, the designer is confronted with low impedance measurements (typically from 1 Ohm to 12 Ohm). These transistors are contained in metal-ceramic packages of which the lead widths vary with power capability. This thesis presents a high-quality fixture design with low impedance TRL calibration standards for characterisation of an LDMOS transistor. Pre-matching networks are used to transform to the low impedance environment. Since these pre-matching networks are independent of the termination impedance, the low impedance port can always be designed to comply with the same dimension as the device which is being measured.

Conception de transistors MOS haute tension en technologie CMOS 0,18 µm sur substrat "silicium sur isolant" (SOI) pour les nouvelles générations de circuits intégrés de puissance. Les circuits intégrés de puissance combinent dans une même puce des fonctions logiques digitales, obtenues par des circuits CMOS, associées à des interrupteurs de puissance de type transistors DMOS. La demande pour des applications de plus en plus complexes nécessite l'utilisation de lithographies plus fines pour augmenter la densité de composants CMOS. L'évolution des technologies CMOS oblige à développer des composants DMOS compatibles dans les circuits intégrés de puissance. Le travail de cette thèse se concentre sur la conception de transistors LDMOS haute tension (120 V) compatibles avec un procédé CMOS 0,18 µm sur substrat " silicium sur isolant " (SOI). Différentes architectures de transistors LDMOS à canal N et P ont été proposées et optimisées en termes de compromis " tenue en tension / résistance passante spécifique " à partir de simulations TCAD à éléments finis. Les performances de ces structures ont été comparées en termes de facteur de mérite Ron×Qg qui est le produit entre charge de grille et résistance passante spécifique, mais aussi en termes d'aire de sécurité. Les meilleurs transistors STI-LDMOS et SJ-LDMOS (à canal N) et R-PLDMOS (à canal P) affichent des performances statiques et dynamiques comparables voire parfois supérieures à celles des composants de puissance de la littérature. Différentes mesures effectuées sur les transistors LDMOS réalisés par ATMEL et comparées aux simulations ont permis de valider les simulations effectuées dans cette thèse.

De tous les circuits qui constituent un système radiofréquence complet, la partie radiofréquence apparaît comme un maillon délicat du système. Parmi les nombreuses fonctions radiofréquences, l'amplificateur de puissance (PA) représente un bloc particulièrement critique de la chaîne d'émission, du fait de sa consommation élevée et des forts niveaux des signaux qu'il doit gérer. Il résulte de ces contraintes que les techniques d'intégration utilisées sont généralement complexes et onéreuses, particulièrement pour la réalisation des éléments inductifs des réseaux de pré-adaptation des transistors de puissance, à partir de fils micro-soudés. Les travaux décrits dans ce manuscrit visent ainsi le développement d'une technologie permettant l'intégration faible coût d'inductances planaires de puissance en mesure de remplacer les fils micro-soudés. Ces travaux ont été réalisés en collaboration avec la société Freescale. Les démonstrateurs présentés mettent donc en œuvre la filière LDMOS sur substrat silicium faiblement résistif. Le mémoire est articulé autour de quatre chapitres. Le premier présente un état de l'art de l'intégration des amplificateurs de puissance RF à partir duquel nous définissons la problématique de cette intégration. Dans le deuxième chapitre, nous traitons des différents mécanismes de pertes présents dans les inductances planaires sur silicium ainsi que de leurs origines. Puis, nous posons les bases de leur modélisation électrique et des simulations électromagnétiques 3D qui seront conduites pour leur optimisation. Le troisième chapitre est ensuite consacré à la description et à l'optimisation de la technologie mise en place au sein du LAAS. Elle met en œuvre, sur un plan métallique qui écrante le silicium sur lequel sont intégrés les transistors, une couche de 65 µm de résine époxy SU8 sur laquelle est implémenté un niveau métallique en cuivre de 35 µm d'épaisseur. Des trous métallisés sont aussi réalisés à travers le niveau SU8 pour les contacts élec triques entre les transistors et le niveau Cu supérieur. Enfin, le quatrième et dernier chapitre traite des caractérisations expérimentales des inductances de test réalisées ainsi que des démonstrateurs intégrant ces inductances directement sur la puce de puissance LDMOS. Dans ce dernier cas, des mesures en forts signaux sont aussi présentées. L'intégration "Above-IC" d'un réseau d'inductances parallèles présentant une valeur finale de 0.2nH pour un facteur de qualité de 40 à 2 GHz et de 58 à 5 Ghz, tout en supportant une densité de courant de 1A/mm², permet d'aboutir à une valeur du rendement de 60% pour un amplificateur RF LDMOS de puissance 50W.

<p>We are in the midst of a technological revolution (popularly known as Industrie 4.0 or 4th Industrial Revolution) where our cars are being equipped with hundreds of sensors that make them safer, homes are becoming smarter, industry yields are at an all-time high, and internet-of-things is a reality. This was largely possible due to the developments in communication, electronics, motor controls, robotics, cyber security, software, efficient power distribution, etc. One of the major propellants of the 4th Industrial revolution is the ever-expanding applications of power electronics devices. All electrical energy will be provided, handled, and consumed through power electronics devices in the near future. Therefore, the reliability of power electronics devices will be instrumental in driving future technological advances. </p> <p> </p> <p><br></p><p>A myriad of devices is categorized as power electronics devices, and in the heart of those devices are the transistors. Although Silicon-based transistors still dominate the power electronics market, a paradigm shift towards wide bandgap semiconductors, such as silicon carbide (SiC), gallium nitride (GaN), beta-gallium oxide etc., is underway. However, realizing the full potential of these devices demands unconventional design, layout, and reliability. </p> <p> </p> <p>In this thesis, we try to establish a generalized model of reliability for power and logic transistors. We start by defining a comprehensive, substrate-, self-heating-, and reliability-aware safe operating area (SOA) that analytically establishes the optimum and self-consistent trade-off among breakdown voltage, power consumption, operating frequency, heat dissipation, and reliability before actual device fabrication. Then we take a deeper look into the reliability of individual transistors (a beta-gallium oxide transistor and a Silicon-based LDMOS), to test the predictions by the safe operating area, using both experiments and simulations. In the beta-gallium oxide transistor, we studied its implementation in a DC-DC voltage converter and concluded that the self-heating is a performance bottleneck and suggested approaches to alleviate it. For the LDMOS transistor, we investigated the hot carrier degradation (HCD) using experiments and simulations. We established that the HCD degradation kinetics is universal, and physics is the same as a classical transistor, despite a complicated geometry. Finally, we studied the correlation between HCD and radiation in LDMOS used in space shuttles, airplanes, etc., to determine its lifetime. </p><p><br></p> <p> </p> <p>We have holistically analyzed the reliability of power transistors by extending the theories of logic transistors in this thesis. Therefore, this thesis takes us a step closer to a generalized reliability model for power transistors by developing a comprehensive and predictive model for the safe operating area, encompassing all sources of stresses (e.g., electrical, thermal, and radiation) it experiences during operation.</p>