This dissertation examines multi-antenna transceiver design over flat-fading wireless channels. Bit Interleaved Coded Modulation (BICM) and MultiLevel Coded Modulation (MLCM) transmitter structures are considered, as well as the used of an optional spatial precoder under slow and quasi-static fading conditions. At the receiver, MultiStage Decoder (MSD) and Iterative Detection and Decoding (IDD) strategies are applied. Precoder, mapper and subcode designs are optimized for different receiver structures over the different antenna and fading scenarios. Under slow and quasi-static channel conditions, fade resistant multi-antenna transmission is achieved through a combination of linear spatial precoding and non-linear multi-dimensional mapping. A time-varying random unitary precoder is proposed, with significant performance gains over spatial interleaving. The fade resistant properties of multidimensional random mapping are also analyzed. For MLCM architectures, a group random labelling strategy is proposed for large antenna systems. The use of complexity constrained receivers in BICM and MLCM transmissions is explored. Two multi-antenna detectors are proposed based on a group detection strategy, whose complexity can be adjusted through the group size parameter. These detectors show performance gains over the the Minimum Mean Squared Error (MMSE)detector in spatially multiplexed systems having an excess number of transmitter antennas. A class of irregular convolutional codes is proposed for use in BICM transmissions. An irregular convolutional code is formed by encoding fractions of bits with different puncture patterns and mother codes of different memory. The code profile is designed with the aid of extrinsic information transfer charts, based on the channel and mapping function characteristics. In multi-antenna applications, these codes outperform convolutional turbo codes under independent and quasi-static fading conditions. For finite length transmissions, MLCM-MSD performance is affected by the mapping function. Labelling schemes such as set partitioning and multidimensional random labelling generate a large spread of subcode rates. A class of generalized Low Density Parity Check (LDPC) codes is proposed, to improve low-rate subcode performance. For MLCM-MSD transmissions, the proposed generalized LDPC codes outperform conventional LDPC code construction over a wide range of channels and design rates.

Au cours des 15 dernières années, des progrès spectaculaires dans l'analyse et la conception des codes définis par des graphes bipartites et dé-codables par des algorithmes itératifs ont permis le développement de systèmes de correction d'erreurs, avec des performances de plus en plus proches la limite théorique de Shannon. Dans ce contexte, un rôle déterminant a été joué par la famille des codes à matrice de parité creuse, appelés codes LDPC (pour " Low-Density Parity-Check ", en anglais), introduit par Gallager au début des années 60 et décrits plus tard en termes de graphes bipartites. Négligés pendant de longues années, ces codes ont été redécouverts à la fin des années 90, après que la puissance du décodage itératif a été mise en évidence grâce à l'invention des Turbo-codes. Ce n'est qu'au début des années 2000 que les techniques nécessaires à l'analyse et l'optimisation des codes LDPC ont été développées, techniques qui ont permis ensuite la construction des codes avec des performances asymptotiques proches de la limite de Shannon. Cette remarquable avancée a motivé l'intérêt croissant de la communauté scientifique et soutenu le transfert rapide de cette technologie vers le secteur industriel. Plus récemment, un intérêt tout particulier a été porté aux codes LDPC définis sur des alphabets non-binaires, grâce notamment à leur meilleure capacité de correction en " longueur finie ". Bien que Gallager ait déjà proposé l'utilisation des alphabets non-binaires, en utilisant l'arithmétique modulaire, les codes LDPC non-binaires définis sur les corps finis n'ont étés étudiés qu'à partir de la fin des années 90. Il a été montré que ces codes offrent de meilleures performances que leurs équivalents binaires lorsque le bloc codé est de longueur faible à modérée, ou lorsque les symboles transmis sur le canal sont eux-mêmes des symboles non-binaires, comme par exemple dans le cas des modulations d'ordre supérieur ou des canaux à antennes multiples.Cependant, ce gain en performance implique un coût non négligeable en termes de complexité de décodage, quipeut entraver l'utilisation des codes LDPC non binaires dans des systèmes réels, surtout lorsque le prix à payer encomplexité est plus important que le gain en performance.Cette thèse traite de l'analyse et de la conception des codes LDPC non binaires pour des canaux à évanouissements. L'objectif principal de la thèse est de démontrer que, outre le gain en performance en termes de capacité de correction, l'emploi des codes LDPC non binaires peut apporter des bénéfices supplémentaires,qui peuvent compenser l'augmentation de la complexité du décodeur. La " flexibilité " et la " diversité "représentent les deux bénéfices qui seront démontrées dans cette thèse. La " flexibilité " est la capacité d'unsystème de codage de pouvoir s'adapter à des débits (rendements) variables tout en utilisant le même encodeuret le même décodeur. La " diversité " se rapporte à sa capacité d'exploiter pleinement l'hétérogénéité du canal de communication.La première contribution de cette thèse consiste à développer une méthode d'approximation de l'évolution de densité des codes LDPC non-binaires, basée sur la simulation Monte-Carlo d'un code " infini ". Nous montrons que la méthode proposée fournit des estimations très fines des performances asymptotiques des codes LDPCnon-binaires et rend possible l'optimisation de ces codes pour une large gamme d'applications et de modèles de canaux.La deuxième contribution de la thèse porte sur l'analyse et la conception de système de codage flexible,utilisant des techniques de poinçonnage. Nous montrons que les codes LDPC non binaires sont plus robustes au poinçonnage que les codes binaires, grâce au fait que les symboles non-binaires peuvent être partialement poinçonnés. Pour les codes réguliers, nous montrons que le poinçonnage des codes non-binaires obéit à des règles différentes, selon que l'on poinçonne des symboles de

Ένα από τα βασικά μειονεκτήματα που παρουσιάζει ο σχεδιασμός και η υλοποίηση LDPC αποκωδικοποιητών είναι η μεγάλη πολυπλοκότητα που παρουσιάζεται σε επίπεδο υλικού εξαιτίας της εσωτερικής διασύνδεσης των μονάδων επεξεργασίας δεδομένων.H αρχιτεκτονική που επιτυγχάνει το μέγιστο επίπεδο παραλληλότητας και κατά συνέπεια είναι πολύ αποδοτική όσον αφορά την ταχύτητα αποκωδικοποίησης, δεν χρησιμοποιείται συχνά εξαιτίας της πολυπλοκότητας του υλικού λόγω των πολλαπλών κυκλωμάτων διασύνδεσης που απαιτεί. Στην παρούσα διπλωματική εργασία προτείνεται μια νέα αρχιτεκτονική για το δίκτυο διασύνδεσης ενώ παράλληλα έχει υλοποιηθεί και ένας αλγόριθμος για την αποδοτική τοποθέτηση των επεξεργαστικών μονάδων σε αυτό το δίκτυο. Επίσης έχει μελετηθεί και η επίδραση μειωμένης μετάδοσης πληροφορίας σε κάθε επανάληψη του αλγορίθμου αποκωδικοποίησης.Το περιβάλλον που χρησιμοποιήθηκε για την εξομοίωση και την παραγωγή των αποτελεσμάτων είναι η πλατφόρμα της Matlab. Η προτεινόμενη αρχιτεκτονική υλοποιήθηκε και εξομοιώθηκε σε κώδικες LDPC που αποτελούν μέρος του προτύπου DVB - S2 (Digital Video Broadcasting).Το συγκεκριμένο πρότυπο, εκτός των άλλων, καθορίζει και τις προδιαγραφές των κωδίκων LDPC που χρησιμοποιούνται κατά την κωδικοποίηση και αποκωδικοποίηση δεδομένων σε συστήματα ψηφιακής δορυφορικής μετάδοσης. Τα αποτελέσματα των εξομοιώσεων σχετίζονται με την πολυπλοκότητα της προτεινόμενης αρχιτεκτονικής σε υλικό αλλά και της απόδοσης (ταχύτητα αποκωδικοποίησης) και συγκρίνονται με την βασική πλήρως παράλληλη αρχιτεκτονική. / One of the main disadvantages of the design and implementation of LDPC decoders is the great complexity presented at the hardware level because of the internal interconnection of processing units. The fully parallel architecture that achieves the maximum level of parallelism and hence is very efficient in terms of speed decoding is not used often because of the hardware complexity due to the multiple interface circuits required. This MSc thesis proposes a new architecture for the network interface and also introduces an algorithm for the efficient placement of the processing units in this network. In addition to that, a modified version of the decoding algorithm has been implemented. The relative advantage of this algorithm is that in each iteration only a percentage of the processing units exchange information with each other. That approach further reduces the hardware complexity and power usage. The environment used to simulate and produce the results is Matlab. The proposed architecture is implemented and simulated in LDPC codes that are part of the standard DVB - S2 (Digital Video Broadcasting). This standard, among other things, determines the specifications of the LDPC codes used in the channel encoding and decoding process in digital satellite transmission systems. The results of the simulations related to the complexity of the proposed architecture in hardware and performance (decoding speed) are compared with the fully parallel architecture.

Thesis (MEng)--Stellenbosch University, 2015. / ENGLISH ABSTRACT: Iterative error correcting codes such as LDPC codes have become prominent in modern forward error correction systems. A particular subclass of LDPC codes known as quasicyclic LDPC codes has been incorporated in numerous high speed wireless communication and video broadcasting standards. These standards feature multiple codes with varying codeword lengths and code rates and require a high throughput. Flexible hardware that is capable of decoding multiple quasi-cyclic LDPC codes is therefore desirable. This thesis investigates binary quasi-cyclic LDPC codes and designs a generic, flexible VHDL decoder. The decoder is further enhanced to automatically select the most likely decoder based on the initial a posterior probability of the parity-check equation syndromes. A software system is developed that generates hardware code for such a decoder based on a small user specification. The system is extended to provide performance simulations for this generated decoder. / AFRIKAANSE OPSOMMING: Iteratiewe foutkorreksiekodes soos LDPC-kodes word wyd gebruik in moderne voorwaartse foutkorreksiestelsels. ’n Subklas van LDPC-kodes, bekend as kwasisikliese LDPC-kodes, word in verskeie hoëspoed-kommunikasie- en video-uitsaaistelselstandaarde gebruik. Hierdie standaarde inkorporeer verskeie kodes van wisselende lengtes en kodetempos, en vereis hoë deurset. Buigsame apparatuur, wat die vermoë het om ’n verskeidenheid kwasisikliese LDPC-kodes te dekodeer, is gevolglik van belang. Hierdie tesis ondersoek binêre kwasisikliese LDPC-kodes, en ontwerp ’n generiese, buigsame VHDL-dekodeerder. Die dekodeerder word verder verbeter om outomaties die mees waarskynlike dekodeerder te selekteer, gebaseer op die aanvanklike a posteriori-waarskynlikheid van die pariteitstoetsvergelykings se sindrome. ’n Programmatuurstelsel word ontwikkel wat die fermware-kode vir so ’n dekodeerder genereer, gebaseer op ’n beknopte gebruikerspesifikasie. Die stelsel word uitgebrei om werksverrigting te simuleer vir die gegenereerde dekodeerder.

abstract: There has been a lot of work on the characterization of capacity and achievable rate regions, and rate region outer-bounds for various multi-user channels of interest. Parallel to the developed information theoretic results, practical codes have also been designed for some multi-user channels such as multiple access channels, broadcast channels and relay channels; however, interference channels have not received much attention and only a limited amount of work has been conducted on them. With this motivation, in this dissertation, design of practical and implementable channel codes is studied focusing on multi-user channels with special emphasis on interference channels; in particular, irregular low-density-parity-check codes are exploited for a variety of cases and trellis based codes for short block length designs are performed. Novel code design approaches are first studied for the two-user Gaussian multiple access channel. Exploiting Gaussian mixture approximation, new methods are proposed wherein the optimized codes are shown to improve upon the available designs and off-the-shelf point-to-point codes applied to the multiple access channel scenario. The code design is then examined for the two-user Gaussian interference channel implementing the Han-Kobayashi encoding and decoding strategy. Compared with the point-to-point codes, the newly designed codes consistently offer better performance. Parallel to this work, code design is explored for the discrete memoryless interference channels wherein the channel inputs and outputs are taken from a finite alphabet and it is demonstrated that the designed codes are superior to the single user codes used with time sharing. Finally, the code design principles are also investigated for the two-user Gaussian interference channel employing trellis-based codes with short block lengths for the case of strong and mixed interference levels. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2015

Submitted by Eduarda Figueiredo (eduarda.ffigueiredo@ufpe.br) on 2015-03-06T15:33:11Z No. of bitstreams: 2 Dissertação de Mestrado - Análise de Códigos LDPC ... - Pedro Melo.pdf: 833849 bytes, checksum: da72453652b3de16d9c3b3abc49d270c (MD5) license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) / Made available in DSpace on 2015-03-06T15:33:11Z (GMT). No. of bitstreams: 2 Dissertação de Mestrado - Análise de Códigos LDPC ... - Pedro Melo.pdf: 833849 bytes, checksum: da72453652b3de16d9c3b3abc49d270c (MD5) license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) Previous issue date: 2012-08-03 / Um canal de comunicação discreto não binário e com memória é apresentado com o objetivo de capturar tanto a informação de decisão suave quanto a correlação temporal de um canal com desvanecimento (DFC) quantizado em 2q níveis de quantização. Mostra-se que o canal discreto pode ser descrito explicitamente em termos de seu processo de entrada binário e processo de ruído 2q-ário. Também é mostrado que o canal é simétrico e admite uma expressão simples para sua capacidade de canal. O processo de ruído é então modelado como um modelo baseado em fila (QB), produzindo uma fonte de ruído markoviano estacionário e ergódico de ordem M com 2q + 2 parâmetros. O DFC é aproximado pelo canal discreto com ruído QB, cujos parâmetros são estimados por um processo iterativo que minimiza a divergência de Kullback-Leibler entre as fontes de ruído do DFC e QB. Os modelos obtidos são usados em esquemas de decodificação LDPC desenvolvidos para o canal discreto com ruído QB, em que se observa um ganho de decodificação quando comparado ao caso sem memória.

In this dissertation the aim was to investigate the usage of algorithms found in computer science and apply suitable algorithms to the problem of decoding multiple-input multipleoutput (MIMO) space-time-frequency block coded signals. It was found that the sphere decoder is a specific implementation of the A* tree search algorithm that is well known in computer science. Based on this knowledge, the sphere decoder was extended to include a priori information in the maximum a posteriori probability (MAP) joint decoding of the STFC block coded MIMO signals. The added complexity the addition of a priori information has on the sphere decoder was investigated and compared to the sphere decoder without a priori information. To mitigate the potential additional complexity several algorithms that determine the order in which the symbols are decoded were investigated. Three new algorithms incorporating a priori information were developed and compared with two existing algorithms. The existing algorithms compared against are sorting based on the norms of the channel matrix columns and the sorted QR decomposition. Additionally, the zero forcing (ZF) and minimum mean squared error (MMSE) decoderswith and without decision feedback (DF) were also extended to include a priori information. The developed method of incorporating a priori information was compared to an existing algorithm based on receive vector translation (RVT). The limitation of RVT to quadrature phase shift keying (QPSK) and binary shift keying (BPSK) constellations was also shown in its derivation. The impact of the various symbol sorting algorithms initially developed for the sphere decoder on these decoders was also investigated. The developed a priori decoders operate in the log domain and as such accept a priori information in log-likelihood ratios (LLRs). In order to output LLRs to the forward error correcting (FEC) code, use of the max-log approximation, occasionally referred to as hard-to-soft decoding, was made. In order to test the developed decoders, an iterative turbo decoder structure was used together with an LDPC decoder to decode threaded algebraic space-time (TAST) codes in a Rayleigh faded MIMO channel. Two variables that have the greatest impact on the performance of the turbo decoder were identified: the hard limit value of the LLRs to the LDPC decoder and the number of independently faded bits in the LDPC code. / Dissertation (MEng)--University of Pretoria, 2013. / gm2014 / Electrical, Electronic and Computer Engineering / unrestricted

In mobile communications, using multiple transmit and receive antennas has shown considerable improvement over single antenna systems. The performance increase can be characterized by more reliable throughput obtained through diversity and the higher achievable data rate through spatial multiplexing. The combination of multiple-input multiple-output (MIMO) wireless technology with the IEEE 802.16e-2005 (WiMAX) standard has been recognized as one of the most promising technologies with the advent of next generation broadband wireless communications. The dissertation introduces a performance evaluation of modern multi-antenna coding techniques on a MIMO-WiMAX platform developed to be capable of simulating space-selective, time-selective and frequency-selective fading conditions, which are known as triply-selective fading conditions. A new concatenated space-time-frequency low-density parity check (LDPC) code is proposed for high performance MIMO systems, where it is shown that the newly defined coding technique outperforms a more conventional approach by concatenating space-time blocks with LDPC codes. The analysis of the coding techniques in realistic mobile environments, as well as the proposed STFC-LDPC code, can form a set of newly defined codes, complementing the current coding schemes defined in the WiMAX standard. / Dissertation (MEng)--University of Pretoria, 2009. / Electrical, Electronic and Computer Engineering / unrestricted

The HF band of radio frequencies, from 3-30 MHz, is unique in its property that it is refracted by the ionosphere. This property allows long distance radio telecommunications around the world without requiring infrastructure. High frequency (HF) communication has been largely superseded by satellite and cellular technologies for day-to-day communications, due to the tight bandwidth constraints and technical difficulties inherent in using it. However there is still a need for HF communications devices where existing infrastructure is not available, such as in remote or polar locations, or in emergency situations due to natural disasters. This research is aimed at the development of an asymmetric HF communications link, with a battery-powered remote unit that transmits a small amount of data to a mains-powered base station. New technologies are identified and evaluated for use in the link, with the aim of reducing the power requirements of the remote unit. Error correction techniques are investigated. Low-density parity check (LDPC) codes, which are powerful codes used for forward error correction, are suggested for use in the link. Quasi-cyclic LDPC codes allow the low-power transmitter unit to use a computationally simple encoder based on feedback shift registers for generating the LDPC block codes cheaply. Semi-blind LDPC turbo equalisation is a powerful technique that can be used at the base station which utilises the structure of the LDPC code to encode the data stream. This equalises a received signal with a minimal amount of training data required, reducing the duty cycle of the remote unit. Hybrid automatic repeat request (HARQ) techniques are also investigated, which increase the throughput of a link when data repeats are required. A novel HARQ techniquewas created and proven to increase throughput in links with noise. As the proposed system may be deployed in remote locations, or locations where it might be difficult or undesirable to erect a proper HF antenna, a selection of buried antennas are characterised. A design for a remote unit is suggested. This unit was manufactured and used to test the capability of inexpensive, low power hardware to implement the proposed remote unit algorithms.

Reliable communication over the noisy channel has become one of the major concerns in the field of digital wireless communications. The low density parity check codes (LDPC) has gained lot of attention recently because of their excellent error-correcting capacity. It was first proposed by Robert G. Gallager in 1960. LDPC codes belong to the class of linear block codes. Near capacity performance is achievable on a large collection of data transmission and storage.In my thesis I have focused on hardware implementation of (3, 6) - regular LDPC codes. A fully parallel decoder will require too high complexity of hardware realization. Partly parallel decoder has the advantage of effective compromise between decoding throughput and high hardware complexity. The decoding of the codeword follows the belief propagation alias probability propagation algorithm in log domain. A 9216 bit, (3, 6) regular LDPC code with code rate ½ was implemented on FPGA targeting Xilinx Virtex 4 XC4VLX80 device with package FF1148. This decoder achieves a maximum throughput of 82 Mbps. The entire model was designed in VHDL in the Xilinx ISE 9.2 environment.