published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy

The integration of high-performance analog and digital circuits leads to an increasing need of new tools compatible for both the digital and analog parts. Unfortunately, the low acceptance of CAD tools in the analog domain presents a serious bottleneck to the fast realization of mixed-signal systems. Due to a higher sensitivity of the electrical performance to layout details, analog designs are much more complicated than digital ones. Process and temperature variations can introduce severe mismatches in devices that are designed to behave identically. These undesirable effects can be alleviated by a symmetric layout. Matching and symmetry in placement and routing in analog circuits are thus of immense importance. / In this thesis, we will present an effective layout method for analog circuits. We consider symmetry constraint, common centroid constraint, device merging and device clustering during the placement step. Symmetric routing will then be performed. In order to have successful routing, we will perform analog-based routability-driven adjustment during the placement process, taking into account for analog circuits that wires are not preferred to be layout on top of active devices. All these concepts were put together in our tool. Experimental results show that we can generate quality analog layout within minutes of time that passes the design rule check, layout-schematic verification and the simulation results are comparable to those of manual design, while a manual design will take a designer a couple of days to generate. / Xiao, Linfu. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 146-154). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract --- p.i / Acknowledgement --- p.ii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Analog Layout Problem --- p.2 / Chapter 1.1.1 --- Analog Circuit Design Flow --- p.3 / Chapter 1.1.2 --- An Example: μA741 Operational Amplifier --- p.5 / Chapter 1.1.3 --- Analog Layout Problem --- p.6 / Chapter 1.2 --- Thesis Contribution and Organization --- p.8 / Chapter 2 --- Background --- p.11 / Chapter 2.1 --- Analog Layout Basics --- p.11 / Chapter 2.1.1 --- Parasitic Effects --- p.12 / Chapter 2.1.2 --- Signal Coupling Effects --- p.13 / Chapter 2.1.3 --- Process Variation Effects --- p.15 / Chapter 2.2 --- Previous Analog Layout Automation Tools --- p.18 / Chapter 2.3 --- Previous Analog Layout Automation Approaches --- p.22 / Chapter 2.3.1 --- Device Generation --- p.23 / Chapter 2.3.2 --- Analog Placement --- p.25 / Chapter 2.3.3 --- Analog Routing --- p.37 / Chapter 3 --- System Overview --- p.45 / Chapter 3.1 --- System Flow Map --- p.45 / Chapter 3.1.1 --- Device Generation --- p.46 / Chapter 3.1.2 --- Analog Placement --- p.49 / Chapter 3.1.3 --- Analog Routing --- p.51 / Chapter 4 --- Analog Placement --- p.53 / Chapter 4.1 --- Introduction --- p.53 / Chapter 4.2 --- Symmetric Feasible Conditions on Sequence Pair --- p.55 / Chapter 4.2.1 --- Properties of Sequence Pair --- p.56 / Chapter 4.2.2 --- Symmetric Feasible Conditions --- p.58 / Chapter 4.3 --- Common Centroid Grid Placement --- p.69 / Chapter 4.3.1 --- Grid Placement Representation --- p.70 / Chapter 4.3.2 --- Common Centroid Feasible Conditions in Grid Sequence --- p.71 / Chapter 4.4 --- Methodology --- p.73 / Chapter 4.4.1 --- Handling Symmetry Constraints --- p.74 / Chapter 4.4.2 --- Device Merging --- p.75 / Chapter 4.4.3 --- Device Clustering --- p.77 / Chapter 4.4.4 --- Enhanced Common Centroid Placement --- p.78 / Chapter 4.4.5 --- Placement Adjustment for Symmetry Groups --- p.82 / Chapter 4.4.6 --- Congestion Aware Placement Expansion --- p.86 / Chapter 4.4.7 --- Types of Moves --- p.87 / Chapter 4.4.8 --- Annealing Schedule and Cost Function --- p.88 / Chapter 5 --- Analog Routing --- p.90 / Chapter 5.1 --- Introduction --- p.90 / Chapter 5.2 --- Methodology --- p.91 / Chapter 5.2.1 --- Symmetry Routing --- p.94 / Chapter 5.2.2 --- Practical Concerns --- p.97 / Chapter 6 --- Layer Assignment --- p.106 / Chapter 6.1 --- Introduction --- p.106 / Chapter 6.1.1 --- Problem Formulation --- p.108 / Chapter 6.1.2 --- Previous Works --- p.109 / Chapter 6.1.3 --- Background --- p.111 / Chapter 6.2 --- Methodology --- p.114 / Chapter 6.2.1 --- Global Conflict-Continuation Graph Construction --- p.114 / Chapter 6.2.2 --- The Modified Two-layer Layer Assignment Scheme --- p.116 / Chapter 6.2.3 --- Stacked Via Problem and Crosstalk --- p.120 / Chapter 6.2.4 --- Max-Cut for planar graph --- p.121 / Chapter 7 --- Experimental Results --- p.128 / Chapter 7.1 --- Results of Analog Placement --- p.129 / Chapter 7.2 --- Results of Layer Assignment --- p.133 / Chapter 7.3 --- Simulation Results --- p.134 / Bibliography --- p.136

To solve these issues, in this thesis the consistent effort in developing a quick tools assisted IC design platform is presented. First, a reconfigurable solution is proposed for some analog/mixed-signal (AMS) system which requires flexibility to a certain extent, such as a reconfigurable RFID solution for different communicating distances. Second, for further demand of increasing the flexibility, a novel approach for ADA is presented, which provides a highly automatic design flow for analog circuits to realize the "SPEC (Specification) in, GDS out" goal. Considering all kinds of higher order effects and uncertainties under deep submicron or even more advanced technologies, reliable design and fastness in processing are the two major concerns instead of the traditional pure optimization for best performance. To get a good balance among performance, reliability and turnaround time, an Application-Specific design flow with in-built knowledge-based algorithms is applied to deal with ADA issues under advanced technologies, which can quickly provide a reliable design with performance good enough to meet the SPECs for common use. / Unlike the highly automatic flow for digital circuits design, analog design automation (ADA) is still far from mature. For mixed-signal applications, analog circuit occupies only a small part on the layout, but the design requires a considerable amount of time and effort, making ADA extremely attractive. However, there are a lot more considerations to cover in analog design flow than its digital counterparts. In addition, the ever downscaling IC means analog circuits have to face more and more small-size effects, insufficient modelings, and the inaccuracy of classic formulas, which are quite difficult to handle. To solve the problem, various tools and methods have been proposed, but all in a digital-like flow, which are trying to develop general algorithms to realize circuit and layout synthesis. Up to now there is still a lot of problems. / Hong, Yang. / Adviser: C.S. Choy. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 140-150). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Present day data processing technology requires very high speed signal processing and data conversion rates. One such application which requires high speed is switched capacitor circuits used in Sigma-Delta modulators. A major active component of switched capacitor circuits is the monolithic operational amplifier(opamp). Because of the relatively poor speed performance of the currently available silicon based technology, such high speed circuits can not be designed. GaAs technology appears to be a promising alternative technology for high speed switched capacitor circuits. One problem with GaAs is the lack of complementary technology. Until now, most of the design of GaAs analog integrated circuits has been implemented using depletion mode n-MESFETs, where operational amplifiers and switched capacitors have been developed by various groups. This thesis develops the techniques for implementation of analog integrated circuits using complementary GaAs Heterojunction Field Effect Transistors(HFETs). Several operational amplifiers have been designed and their performance studied via simulation. The designs studied predict superior high frequency performance for C-HFETs over conventional GaAs MESFET and Silicon CMOS technology. The opamp designs are currently being implemented at Oregon State University for fabrication in the future. / Graduation date: 1993

High-performance, high-frequency operational transconductance amplifiers (OTAs) are very important elements in the design of high-frequency continuous-time integrated analog signal processing circuits, because resistors, inductors, integrators, mutators, buffers, multipliers, and filters can be built by OTAs and capacitors. The critical considerations for OTA design are linearity, tuning, frequency response, output impedance, power supply rejection (PSR) and common-mode rejection (CMR). For linearity considerations, two different methods are proposed. One uses cross-coupled pairs (CMOS or NMOS), producing OTAs with very high linearity but either the input range is relatively small or the CMR to asymmetrical inputs is poor. Another employs multiple differential pairs (current addition or subtraction), producing OTAs with high linearity over a very large input range. So, there are tradeoffs among the critical considerations. For different applications, different OTAs should be selected. For consideration of frequency response, the first reported GaAs OTA was designed for achieving very-high-frequency performance, instead of using AC compensation techniques. GaAs is one of the fastest available technologies, but it was new and less mature than silicon when we started the design in 1989. So, there were several issues, such as low output impedance, no P-channel devices, and Schottky clamp. To overcome these problems, new techniques are proposed, and the designed OTA has comparable performance to a CMOS OTA. For PSR and CMR considerations, a fully balanced circuit structure is employed with a common-mode feedback (CMF) circuit used to stabilize the DC output voltages. To reduce the interaction of the operation of CMF and tuning of OTAs, three improved versions of the CMF circuits used in operational amplifiers are proposed. With the designed OTAs, a I GHz GaAs inductor with small parasitics is designed using the proposed procedure to reduce high-frequency effects. Two CMOS high-order, high-frequency filters are designed: one in cascade structure and one in LC ladder form. Also, a 200 MHz third-order elliptic GaAs filter is designed with special consideration of very-high-frequency parasitics. All circuits were fabricated and measured. The experimental results were used to verify the designs.

At this time the synthesis of reversible circuits for quantum computing is an active area of research. In the most restrictive quantum computing models there are no ancilla lines and the quantum cost, or latency, of performing a reversible form of the AND gate, or Toffoli gate, increases exponentially with the number of input variables. In contrast, the quantum cost of performing any combination of reversible EXOR gates, or CNOT gates, on n input variables requires at most O(n2/log2n) gates. It was under these conditions that EXOR-AND-EXOR, or EPOE, synthesis was developed. In this work, the GF(2) logic theory used in EPOE is expanded and the concept of an EXOR-AND product transform is introduced. Because of the generality of this logic theory, it is adapted to EXOR-AND-OR, or SPOE, synthesis. Three heuristic spectral logic synthesis algorithms are introduced, implemented in a program called XAX, and compared with previous work in classical logic circuits of up to 26 inputs. Three linear reversible circuit methods are also introduced and compared with previous work in linear reversible logic circuits of up to 100 inputs.

This dissertation focuses on wideband circuit design and implementation issues up to 10GHz based on the direct conversion architecture in the CMOS and SiGe BiCMOS technologies. The dissertation consists of two parts: One, implementation of a RF front-end receiver for an ultra-wideband system and, two, implementation of a local oscillation (LO) signal for a GSM/WCDMA multiband application. For emerging ultra-wideband (UWB) applications, the key active components in the RF front-end receiver were designed and implemented in 0.18um SiGe BiCMOS process. The design of LNA, which is the critical circuit block for both systems, was analyzed in terms of noise, linearity and group delay variation over an extemely wide bandwidth. Measurements are demonstrated for an energy-thrifty UWB receiver based on an MB-OFDM system covering the full FCC-allowed UWB frequency range. For multiband applications such as a GSM/WCDMA dual-band application, the design of wideband VCO and various frequency generation blocks are investigated as alternatives for implementation of direct conversion architecture. In order to reduce DC-offset and LO pulling phenomena that degrade performance in a typical direct conversion scheme, an innovative fractional LO signal generator was implemented in a standard CMOS process. A simple analysis is provided for the loop dynamics and operating range of the design as well as for the measured results of the factional LO signal generator.

With the probable end of Moore's Law in the near future, and with advances in nanotechnology, new forms of computing are likely to become available. Reversible computing is one of these possible future technologies, and it employs reversible circuits. Reversible circuits in a classical form have the potential for lower power consumption than existing technology, and in a quantum form permit new types of encryption and computation. One fundamental challenge in synthesizing the most general type of reversible circuit is that the storage space for fully specifying input-output descriptions becomes exponentially large as the number of inputs increases linearly. Certain restricted classes of reversible circuits, namely affine-linear, linear, and permutation circuits, have much more compact representations. The synthesis methods which operate on these restricted classes of reversible circuits are capable of synthesizing circuits with hundreds of inputs. In this thesis new types of synthesis methods are introduced for affine-linear, linear, and permutation circuits, as well as a synthesizable HDL design for a scalable, systolic processor for linear reversible circuit synthesis.

University of Macau / Faculty of Science and Technology / Department of Electrical and Electronics Engineering

The performance of analog integrated circuits is dependent on the technology. Digital circuits are scalable in nature, and the same circuit can be scaled from one technology to another with improved performance. But, in analog integrated circuits, the circuit components must be re-designed to maintain the desired performance across different technologies. Moreover, in the case of digital circuits, minimum feature-size (short channel length) devices can be used for better performance, but analog circuits are still being designed using channel lengths larger than the minimum feature sizes. The research in this thesis is aimed at understanding the impact of technology scaling and short channel length devices on the performance of analog integrated circuits. The operational amplifier (op amp) is chosen as an example circuit for investigation. The performance of the conventional op amps are studied across different technologies for short channel lengths, and techniques to develop technology-independent op amp architectures have been proposed. In this research, three op amp architectures have been developed whose performance is relatively independent of the technology and the channel length. They are made scalable, and the same op amp circuits are scaled from a 0.25 um CMOS onto a 0.18 um CMOS technology with the same components. They are designed to achieve large small-signal gain, constant unity gain-bandwidth frequency and constant phase margin. They are also designed with short channel length transistors. Current feedback, gm-boosted, CMOS source followers are also developed, and they are used in the buffered versions of these op amps.