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published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy

The integration of high-performance analog and digital circuits leads to an increasing need of new tools compatible for both the digital and analog parts. Unfortunately, the low acceptance of CAD tools in the analog domain presents a serious bottleneck to the fast realization of mixed-signal systems. Due to a higher sensitivity of the electrical performance to layout details, analog designs are much more complicated than digital ones. Process and temperature variations can introduce severe mismatches in devices that are designed to behave identically. These undesirable effects can be alleviated by a symmetric layout. Matching and symmetry in placement and routing in analog circuits are thus of immense importance. / In this thesis, we will present an effective layout method for analog circuits. We consider symmetry constraint, common centroid constraint, device merging and device clustering during the placement step. Symmetric routing will then be performed. In order to have successful routing, we will perform analog-based routability-driven adjustment during the placement process, taking into account for analog circuits that wires are not preferred to be layout on top of active devices. All these concepts were put together in our tool. Experimental results show that we can generate quality analog layout within minutes of time that passes the design rule check, layout-schematic verification and the simulation results are comparable to those of manual design, while a manual design will take a designer a couple of days to generate. / Xiao, Linfu. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 146-154). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract --- p.i / Acknowledgement --- p.ii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Analog Layout Problem --- p.2 / Chapter 1.1.1 --- Analog Circuit Design Flow --- p.3 / Chapter 1.1.2 --- An Example: μA741 Operational Amplifier --- p.5 / Chapter 1.1.3 --- Analog Layout Problem --- p.6 / Chapter 1.2 --- Thesis Contribution and Organization --- p.8 / Chapter 2 --- Background --- p.11 / Chapter 2.1 --- Analog Layout Basics --- p.11 / Chapter 2.1.1 --- Parasitic Effects --- p.12 / Chapter 2.1.2 --- Signal Coupling Effects --- p.13 / Chapter 2.1.3 --- Process Variation Effects --- p.15 / Chapter 2.2 --- Previous Analog Layout Automation Tools --- p.18 / Chapter 2.3 --- Previous Analog Layout Automation Approaches --- p.22 / Chapter 2.3.1 --- Device Generation --- p.23 / Chapter 2.3.2 --- Analog Placement --- p.25 / Chapter 2.3.3 --- Analog Routing --- p.37 / Chapter 3 --- System Overview --- p.45 / Chapter 3.1 --- System Flow Map --- p.45 / Chapter 3.1.1 --- Device Generation --- p.46 / Chapter 3.1.2 --- Analog Placement --- p.49 / Chapter 3.1.3 --- Analog Routing --- p.51 / Chapter 4 --- Analog Placement --- p.53 / Chapter 4.1 --- Introduction --- p.53 / Chapter 4.2 --- Symmetric Feasible Conditions on Sequence Pair --- p.55 / Chapter 4.2.1 --- Properties of Sequence Pair --- p.56 / Chapter 4.2.2 --- Symmetric Feasible Conditions --- p.58 / Chapter 4.3 --- Common Centroid Grid Placement --- p.69 / Chapter 4.3.1 --- Grid Placement Representation --- p.70 / Chapter 4.3.2 --- Common Centroid Feasible Conditions in Grid Sequence --- p.71 / Chapter 4.4 --- Methodology --- p.73 / Chapter 4.4.1 --- Handling Symmetry Constraints --- p.74 / Chapter 4.4.2 --- Device Merging --- p.75 / Chapter 4.4.3 --- Device Clustering --- p.77 / Chapter 4.4.4 --- Enhanced Common Centroid Placement --- p.78 / Chapter 4.4.5 --- Placement Adjustment for Symmetry Groups --- p.82 / Chapter 4.4.6 --- Congestion Aware Placement Expansion --- p.86 / Chapter 4.4.7 --- Types of Moves --- p.87 / Chapter 4.4.8 --- Annealing Schedule and Cost Function --- p.88 / Chapter 5 --- Analog Routing --- p.90 / Chapter 5.1 --- Introduction --- p.90 / Chapter 5.2 --- Methodology --- p.91 / Chapter 5.2.1 --- Symmetry Routing --- p.94 / Chapter 5.2.2 --- Practical Concerns --- p.97 / Chapter 6 --- Layer Assignment --- p.106 / Chapter 6.1 --- Introduction --- p.106 / Chapter 6.1.1 --- Problem Formulation --- p.108 / Chapter 6.1.2 --- Previous Works --- p.109 / Chapter 6.1.3 --- Background --- p.111 / Chapter 6.2 --- Methodology --- p.114 / Chapter 6.2.1 --- Global Conflict-Continuation Graph Construction --- p.114 / Chapter 6.2.2 --- The Modified Two-layer Layer Assignment Scheme --- p.116 / Chapter 6.2.3 --- Stacked Via Problem and Crosstalk --- p.120 / Chapter 6.2.4 --- Max-Cut for planar graph --- p.121 / Chapter 7 --- Experimental Results --- p.128 / Chapter 7.1 --- Results of Analog Placement --- p.129 / Chapter 7.2 --- Results of Layer Assignment --- p.133 / Chapter 7.3 --- Simulation Results --- p.134 / Bibliography --- p.136

The growing interest in programmable analog circuits has led to the development of Field Programmable Analog Arrays (FPAAs). An FPAA consists of: 1) a programmable cell that can be reconfigured to perform several analog functions. 2) an architecture that interconnects a number of copies of the programmable cell. In this thesis, the full monolithic circuit implementation of the analog part of the programmable cell is presented. Chapter I gives an introduction to the idea of FPAA and introduces the FPAA architecture and the cell block diagram. Chapter II deals with the design and verification of a differential current-mode four-quadrant multiplier. The weighting-summing circuit with the normalizing stage is discussed in Chapter III. Chapter IV presents the design of a current-mode low-voltage programmable integratorgain circuit. Programmability was achieved by changing the bias current in the designed circuits; no analog switches were used in the signal path. This shows no effect on the performance of the circuits. The presented programming method, however, relies on the availability of a programmable current source with a storage capability. The design of this current source is discussed in chapter V. Conclusions are summarized in Chapter VI. The presented designs throughout the whole thesis were supported by detailed analytical derivations with the necessary SPICE simulations to verify the performance.

Existing linearisation methods were examined to establish the requirements for a wideband power amplifier model. A range of memoryless models were investigated, in particular polynomial models. No suitable memoryless models were found. The shortcomings of the models were analysed and directions for future investigations presented. / thesis (MEng(ElectronicsEngineering))--University of South Australia, 2003.

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Existing linearisation methods were examined to establish the requirements for a wideband power amplifier model. A range of memoryless models were investigated, in particular polynomial models. No suitable memoryless models were found. The shortcomings of the models were analysed and directions for future investigations presented. / Thesis (MEng(ElectronicsEngineering))--University of South Australia, 2003

Existing linearisation methods were examined to establish the requirements for a wideband power amplifier model. A range of memoryless models were investigated, in particular polynomial models. No suitable memoryless models were found. The shortcomings of the models were analysed and directions for future investigations presented. / thesis (MEng(ElectronicsEngineering))--University of South Australia, 2003.

Existing linearisation methods were examined to establish the requirements for a wideband power amplifier model. A range of memoryless models were investigated, in particular polynomial models. No suitable memoryless models were found. The shortcomings of the models were analysed and directions for future investigations presented. / Thesis (MEng(ElectronicsEngineering))--University of South Australia, 2003