For the first method, a novel linearization scheme for CMOS double-balanced mixer based on the use of multi-bias dual-gate transistors is presented. In this technique, two intermodulation distortion components with proper phase relationship, generated by devices operating at different bias conditions, are added together to cancel each other for the improvement of mixer's linearity. The measured performance of a fabricated CMOS mixer operating at RF frequency of 2.45GHz and LO frequency of 2.35GHz is demonstrated. Over 35dB of IMD reduction is achieved by the proposed method under optimal biasing condition. / In the second design, a novel linearization scheme for cascode amplifier based upon capacitive feedback is presented. This method involves the optimal design of the feedback network for IMD reduction. By using Volterra series analysis, expression for IMD products is derived and the corresponding circuit parameters for optimized linearity are obtained. For experimental verification, CMOS cascode amplifiers are designed and fabricated to operate at 2.45GHz with supply voltage of 2V. By measurement, IIP3 is improved of almost 7dB by using the proposed feedback technique. The performance dependency of the fabricated amplifiers under different bias conditions is also examined. The results indicate that the proposed technique can offer low sensitivity to the variation of process parameters. / Linearity is one of the major requirements in modern communication systems due to the limited channel spacing. In the past years, various linearization schemes have been studied extensively for RF circuit design such as low-noise amplifiers and power amplifiers. These techniques offer IMD reduction at the expense of circuit complexity. In the last decade, much effort has been devoted to the development of single-chip RF transceiver using sub-micron CMOS technology. This thesis presents three simple and effective linearization techniques for CMOS mixer and amplifier design. They are experimentally verified by circuit fabrication based on 0.35mum CMOS process. / The last approach combines the advantages of source degeneration and the capacitive feedback for cascode amplifier linearization. Experiments are performed on CMOS amplifiers operating at 2.45GHz, and more than 11dB of IIP3 enhancement is observed. / Au Yeung, Chung Fai. / "August 2007." / Adviser: Chang Kwok Keung. / Source: Dissertation Abstracts International, Volume: 69-02, Section: B, page: 1189. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (p. 153-161). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract in English and Chinese. / School code: 1307.

by Tse Man Siu. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1988. / Bibliography: leaves 203-210.

Leung Chi-Shuen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 82-89). / Abstracts in English and Chinese. / Chapter Chapter 1 --- Introduction --- p.1 / Chapter Chapter 2 --- Review of Linearization Techniques --- p.4 / Chapter 2.1 --- Feedforward --- p.5 / Chapter 2.2 --- Feedback --- p.7 / Chapter 2.3 --- Predistortion --- p.10 / Chapter Chapter 3 --- The Volterra Series Method for Nonlinear Analysis --- p.12 / Chapter 3.1 --- Volterra Series Method --- p.13 / Chapter 3.2 --- Nonlinear Transfer Function --- p.14 / Chapter 3.3 --- Weakly Nonlinear Approximation --- p.18 / Chapter 3.4 --- Nonlinear Modeling --- p.19 / Chapter 3.5 --- Determination of Nonlinear Transfer Function --- p.22 / Chapter Chapter 4 --- Manifestation of Nonlinear Behavior --- p.25 / Chapter 4.1 --- Two-Tone Volterra Series Analysis --- p.25 / Chapter 4.2 --- Harmonic Distortion --- p.28 / Chapter 4.3 --- AM/AM and AM/PM --- p.29 / Chapter 4.4 --- Intermodulation Distortion --- p.31 / Chapter Chapter 5 --- The Generalized Baseband Signal Injection Method --- p.33 / Chapter 5.1 --- Generalized Baseband Signal Injection Method (GM) --- p.34 / Chapter 5.2 --- Application of GM to Predistorter-Amplifier Linearization --- p.38 / Chapter 5.2.1 --- Case 1: Standalone Amplifier without Injection --- p.40 / Chapter 5.2.2 --- Case 2: Injection to Amplifier Only --- p.41 / Chapter 5.2.3 --- Case 3: Injection to Diode Predistorter Only --- p.41 / Chapter 5.2.4 --- Case 4: Injection to Both Diode Predistorter and Amplifier --- p.42 / Chapter 5.3 --- Application of GM to Multi-Stage Amplifier Linearization --- p.43 / Chapter 5.3.1 --- Case 1: Amplifying System with No Signal Injection --- p.46 / Chapter 5.3.2 --- Case 2: Amplifying System with Single Injection Point --- p.47 / Chapter 5.3.3 --- Case 3: Amplifying System with Two Injection Points --- p.48 / Chapter Chapter 6 --- Experimental Setup and Measurements --- p.50 / Chapter 6.1 --- Experimental Setup --- p.51 / Chapter 6.1.1 --- Diode Predistorter --- p.51 / Chapter 6.1.2 --- Small Signal Amplifier --- p.54 / Chapter 6.1.3 --- Medium Power Amplifier --- p.58 / Chapter 6.1.4 --- Baseband Signal Generation Circuit --- p.61 / Chapter 6.1.5 --- Baseband Amplifiers --- p.63 / Chapter 6.2 --- Linearization of Amplifier with Predistortion Circuitry --- p.65 / Chapter 6.2.1 --- Two-Tone Test --- p.65 / Chapter 6.2.2 --- Vector Signal Test --- p.68 / Chapter 6.2.3 --- Dynamic Range Evaluation --- p.70 / Chapter 6.3 --- Linearization of Multi-Stage Amplifying System --- p.71 / Chapter 6.3.1 --- Determination of Transfer and Gain Coefficients --- p.71 / Chapter 6.3.2 --- Two-Tone Test --- p.74 / Chapter 6.3.3 --- Vector Signal Test --- p.77 / Chapter 6.3.4 --- Dynamic Range Evaluation --- p.79 / Chapter Chapter 7 --- Conclusion and Future Work --- p.80 / References --- p.82 / Author's Publications --- p.90

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1977. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / by Robert Philip Gilmore. / M.S.

Fan Chun Wah. / "March 2002." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (p. [140]-148). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

To solve these issues, in this thesis the consistent effort in developing a quick tools assisted IC design platform is presented. First, a reconfigurable solution is proposed for some analog/mixed-signal (AMS) system which requires flexibility to a certain extent, such as a reconfigurable RFID solution for different communicating distances. Second, for further demand of increasing the flexibility, a novel approach for ADA is presented, which provides a highly automatic design flow for analog circuits to realize the "SPEC (Specification) in, GDS out" goal. Considering all kinds of higher order effects and uncertainties under deep submicron or even more advanced technologies, reliable design and fastness in processing are the two major concerns instead of the traditional pure optimization for best performance. To get a good balance among performance, reliability and turnaround time, an Application-Specific design flow with in-built knowledge-based algorithms is applied to deal with ADA issues under advanced technologies, which can quickly provide a reliable design with performance good enough to meet the SPECs for common use. / Unlike the highly automatic flow for digital circuits design, analog design automation (ADA) is still far from mature. For mixed-signal applications, analog circuit occupies only a small part on the layout, but the design requires a considerable amount of time and effort, making ADA extremely attractive. However, there are a lot more considerations to cover in analog design flow than its digital counterparts. In addition, the ever downscaling IC means analog circuits have to face more and more small-size effects, insufficient modelings, and the inaccuracy of classic formulas, which are quite difficult to handle. To solve the problem, various tools and methods have been proposed, but all in a digital-like flow, which are trying to develop general algorithms to realize circuit and layout synthesis. Up to now there is still a lot of problems. / Hong, Yang. / Adviser: C.S. Choy. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 140-150). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

模擬電路版圖設計是一個非常複雜和耗時的過程。通常情況下，設計一個高質量的模擬電路版圖需要電子工程師花費幾週甚至更長的時間。模擬電路的電子特性對於電路的細節設計非常敏感，因此，減小電路中的失配現象成為模擬電路版圖設計中一個非常重要的課題。 / 在本論文中，我們提出了一系列實際的佈局技術，來降低電路的失配並提高繞線的成功率。我們可以非常容易的將這些技術整合至一個完整的模擬佈局和佈線的工具中，此工具可以在幾分鐘內生成一個完整的、高質量的模擬電路版圖。同時，該版圖能夠通過設計規則驗證（DRC）和佈局與電路設計一致性檢測（LVS）。模擬結果顯示，它的電路性能能夠與達到甚至超出手工設計的電路版圖。我們的論文主要作出了以下兩方面貢獻。 / 1. 平衡佈局：對於模擬電路中的電子元器件，如電容、電阻、晶體管等進行一維和二維的平衡佈局。電子工程師可以根據不同的設計需求，通過選擇不同的佈局參數來改變電路的佈局排列方式。同時，在模擬退火算法中，我們著重考慮了器件間的匹配以生成高質量的模擬電路佈局。 / 2. 消除阻塞的電路佈局：在模擬電路設計中，我們期望盡量避免在電子元器件密度較高的區域進行繞線。因此，我們需要在電路佈局設計過程中在電子元器件間留有足夠的佈線空間。為達到這個目標，我們提出了更精確的阻塞估計方法和版圖拓展方法，使其能夠生成一個高質量、高繞線成功率的電路佈局結果。 / 為了驗證生成的電路版圖的質量和匹配特性，我們利用蒙地卡羅方法來模擬電路中的製程偏差和失配特性。實驗結果顯示，我們的工具可以在幾分鐘內自動生成高質量的電路版圖，與人工設計通常需要花費數日至數週相比，設計時間大幅縮短，同時電路的匹配特性得以提升。 / Analog layout design is a complicated and time-consuming process. It often takes couples of weeks for the layout designers to generate a qualied layout. The elec-trical properties of analog circuit are very sensitive to the layout details, and mis-match reduction becomes a very important issue in analog layout design. / In this thesis, we will present some practical placement techniques to reduce mismatch and improve routability. These techniques can be easily integrated into a complete analog placement and routing ow, which can produce in just a few min-utes a complete and high quality layout for analog circuits that passes the design rule check, layout-schematic check and with performance veried by simulations. The contents of this thesis will focus on the following two issues: / (1) Symmetry Placement: We consider symmetric placement of transistors, re-sistors and capacitors, which includes 1-D symmetry and 2-D symmetry (or called common centroid). Different symmetric placement congurations, derived accord-ing to the practical needs in analog design, are considered for the matching devices in the simulated annealing engine of the placer in order to generate a placement with high quality. / (2) Congestion-driven Placement: In analog design, wires are preferred not be routed over active devices, so we need to leave enough spaces properly for routing between the devices during the placement process. To achieve this, we explore congestion estimation and layout expansion during the placement step in order to produce a good and routable solution. / In order to verify the quality of the generated layouts in terms of mismatch, we will run Monte Carlo simulations on them with variations in process and mismatch. Experiments show that our methodology can generate high quality layout automatically in just a few minutes while manual design may take couples of days. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Cui, Guxin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Abstracts also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Physical Design --- p.2 / Chapter 1.3 --- Analog Placement --- p.4 / Chapter 1.3.1 --- Methodologies of Analog Placement --- p.4 / Chapter 1.3.2 --- Symmetry Constraints of Analog Placement --- p.5 / Chapter 1.4 --- Process Variation and Layout Mismatch --- p.6 / Chapter 1.4.1 --- Process Variation --- p.6 / Chapter 1.4.2 --- Random Mismatch and Systematic Mismatch --- p.7 / Chapter 1.5 --- Monte Carlo Simulation Procedure --- p.9 / Chapter 1.6 --- Problem Formulation of Placement --- p.9 / Chapter 1.7 --- Motivations --- p.10 / Chapter 1.8 --- Contributions --- p.11 / Chapter 1.9 --- Thesis Organization --- p.12 / Chapter 2 --- Literature Review on Analog Placement --- p.13 / Chapter 2.1 --- Topological Representations Handling Symmetry Constraints --- p.14 / Chapter 2.1.1 --- Symmetry within the Sequence-Pair (SP) Representation . --- p.14 / Chapter 2.1.2 --- Block Placement with Symmetry Constraints Based on the O-Tree Non-Slicing Representation --- p.16 / Chapter 2.1.3 --- Placement with Symmetry Constraints for Analog Layout Design Using TCG-S --- p.17 / Chapter 2.1.4 --- Modeling Non-Slicing Floorplans with Binary Trees --- p.19 / Chapter 2.1.5 --- Segment Trees Handle Symmetry Constraints --- p.20 / Chapter 2.1.6 --- Center-based Corner Block List --- p.22 / Chapter 2.2 --- Other Works on Analog Placement Constraints --- p.25 / Chapter 2.2.1 --- Deterministic Analog Placement with Hierarchically Bounded Enumeration and Enhanced Shape Functions --- p.25 / Chapter 2.2.2 --- Analog Placement Based on Symmetry-Island Formulation --- p.27 / Chapter 2.2.3 --- Heterogeneous B*-Trees for Analog Placement with Symmetry and Regularity Considerations --- p.28 / Chapter 2.3 --- Summary --- p.31 / Chapter 3 --- Common-Centroid Analog Placement --- p.32 / Chapter 3.1 --- Problem Formulation --- p.33 / Chapter 3.2 --- Overview of Our Work --- p.35 / Chapter 3.3 --- Handling Common Centroid Constraints in Different Devices --- p.37 / Chapter 3.3.1 --- Common Centroid Placement of Resistors --- p.38 / Chapter 3.3.2 --- Common Centroid Placement of Transistors --- p.44 / Chapter 3.3.3 --- Common Centroid Placement of Capacitors --- p.47 / Chapter 3.4 --- Congestion Estimation and Layout Expansion --- p.50 / Chapter 3.4.1 --- Blockage-Aware Congestion Estimation --- p.51 / Chapter 3.4.2 --- Layout Expansion --- p.56 / Chapter 3.5 --- Simulated Annealing --- p.59 / Chapter 3.5.1 --- Types of Moves --- p.59 / Chapter 3.5.2 --- Handling Devices in Symmetry Group --- p.59 / Chapter 3.5.3 --- Cost Function of Simulated Annealing --- p.61 / Chapter 3.6 --- Summary --- p.62 / Chapter 4 --- Experimental Results and Monte-Carlo Simulations --- p.64 / Chapter 4.1 --- Study of Congestion-driven Layout Expansion --- p.64 / Chapter 4.2 --- Monte Carlo Simulations --- p.70 / Chapter 4.2.1 --- Devices Modeling --- p.70 / Chapter 4.2.2 --- Study of Layouts with and without Symmetry Groups --- p.71 / Chapter 4.2.3 --- Study of Layouts with and without Self-Symmetry Devices --- p.73 / Chapter 4.2.4 --- Study of Layouts with Different Number of Symmetry Groups --- p.74 / Chapter 4.2.5 --- Study of Large and Small Size Capacitors Array --- p.76 / Chapter 4.3 --- Comparison of Automatic and Manual Layouts using Monte Carlo Simulations --- p.79 / Chapter 5 --- Conclusion --- p.86 / Bibliography --- p.87

Au-Yeung Chung-Fai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 85-91). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Contents --- p.iv / Chapter Chapter 1 --- Introduction --- p.1 / Chapter Chapter 2 --- Basic Theory of Mixer --- p.6 / Chapter 2.1 --- Definition of mixer's electrical parameters --- p.8 / Chapter 2.2.1 --- Conversion gain --- p.8 / Chapter 2.2.2 --- Port-to-port isolation --- p.8 / Chapter 2.2.3 --- Noise figure --- p.9 / Chapter 2.2.4 --- 1-dB compression point (P1dB) --- p.11 / Chapter 2.2.5 --- 2nd order intercept point (IP2) --- p.11 / Chapter 2.2.6 --- 3rd order intercept point (IP3) --- p.12 / Chapter 2.2.7 --- Blocking dynamic range (BDR) --- p.12 / Chapter 2.2.8 --- Spurious free dynamic range (SFDR) --- p.12 / Chapter 2.2 --- Review of mixer architectures --- p.13 / Chapter 2.2.1 --- Diode mixer --- p.13 / Chapter 2.2.2 --- Dual-gate mxer --- p.14 / Chapter 2.2.3 --- Singly balanced mixer --- p.15 / Chapter 2.2.4 --- Doubly balanced dual-gate mixer --- p.16 / Chapter 2.2.5 --- Gilbert cell mixer --- p.18 / Chapter Chapter 3 --- CMOS Doubly Balanced Dual-Gate Mixer Design --- p.20 / Chapter 3.1 --- Design and Analysis --- p.20 / Chapter 3.1.1 --- Principle of operation --- p.20 / Chapter 3.1.2 --- Doubly balanced dual-gate mixer --- p.23 / Chapter 3.1.3 --- Common source output buffer --- p.25 / Chapter 3.1.4 --- Design example and simulation results --- p.26 / Chapter 3.2 --- IC Layout --- p.29 / Chapter 3.2.1 --- Multi-fingers transistor --- p.29 / Chapter 3.2.2 --- Matched transistor --- p.31 / Chapter 3.2.3 --- Match resistor --- p.32 / Chapter 3.2.4 --- Layout of CMOS doubly balanced dual-gate mixer --- p.33 / Chapter Chapter 4 --- Review of Mixer Linearization Techniques --- p.34 / Chapter 4.1 --- Source degeneration --- p.34 / Chapter 4.2 --- Feed-forward system --- p.36 / Chapter 4.3 --- Predistortion --- p.38 / Chapter 4.4 --- Difference-frequency (low-frequency) injection technique --- p.41 / Chapter Chapter 5 --- Mixer Linearization 一 Low Frequency Signal Injection --- p.44 / Chapter 5.1 --- Mixer's linearity --- p.44 / Chapter 5.2 --- Low-frequency signal injection method --- p.46 / Chapter 5.2.1 --- Single-injection scheme --- p.49 / Chapter 5.2.2 --- Dual-injection scheme --- p.50 / Chapter 5.2.3 --- Effect of gain error --- p.51 / Chapter 5.2.4 --- Bandwidth lim itation --- p.52 / Chapter Chapter 6 --- Experiments and Results --- p.55 / Chapter 6.1 --- CMOS doubly balanced dual-gate mixer --- p.55 / Chapter 6.1.1 --- Conversion gain --- p.56 / Chapter 6.1.2 --- Port-to-port isolation --- p.57 / Chapter 6.1.3 --- No ise figure --- p.60 / Chapter 6.1.4 --- 1-dB compression point --- p.61 / Chapter 6.1.5 --- 3rd order intercept point --- p.62 / Chapter 6.2 --- Low-frequency signal injection method --- p.63 / Chapter 6.2.1 --- Measurement result: single-injection scheme --- p.64 / Chapter 6.2.2 --- Measurement result: dual-injection scheme --- p.66 / Chapter Chapter 7 --- Conclusions and Recommendations for Future Work --- p.68 / Chapter 7.1 --- Conclusions --- p.68 / Chapter 7.2 --- Recommendations for future work --- p.69 / Appendix --- p.70 / Chapter A1 --- CMOS technology --- p.70 / Chapter A1.1 --- MOSFET structure --- p.70 / Chapter A1.2 --- CMOS n-well process --- p.71 / Chapter A1.3 --- MOSFET device modeling --- p.74 / Chapter A1.4 --- Channel length modulation --- p.78 / Chapter A1.5 --- Body effect --- p.78 / Chapter A2 --- Mixer's nonlinearity analysis --- p.79 / Chapter A2.1 --- First-order effect --- p.79 / Chapter A2.2 --- Second-order effect --- p.80 / Chapter A2.3 --- Third-order effect --- p.81 / Chapter A2.4 --- Nonlinear IF spectrum --- p.82 / Chapter A3 --- Artificial IMD3 produced by low-frequency signal injection --- p.83 / Author's Publication List --- p.85 / References --- p.86

Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor (SC) circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low voltage conditions. There exist three techniques to solve the problem, but with their own limitations. Multi-threshold process increases cost. Boosted clock will cause life time reliability issues. Switched-opamp slows down the speed of operation. A new low-voltage SC technique without special process and boosted-clock is studied to overcome these drawbacks. To verify the speed advantage of the new scheme over the switched-opamp technique, a 10-bit 20 MS/s pipeline A/D converter operating at 1.5 V supply voltage was designed. A new pseudo-differential structure was proposed and some relevant design issues are discussed. Circuit implementations and layout floorplan are described. All designs are based on Matlab, SWITCAP and Hspice simulation. / Graduation date: 2000

Present day data processing technology requires very high speed signal processing and data conversion rates. One such application which requires high speed is switched capacitor circuits used in Sigma-Delta modulators. A major active component of switched capacitor circuits is the monolithic operational amplifier(opamp). Because of the relatively poor speed performance of the currently available silicon based technology, such high speed circuits can not be designed. GaAs technology appears to be a promising alternative technology for high speed switched capacitor circuits. One problem with GaAs is the lack of complementary technology. Until now, most of the design of GaAs analog integrated circuits has been implemented using depletion mode n-MESFETs, where operational amplifiers and switched capacitors have been developed by various groups. This thesis develops the techniques for implementation of analog integrated circuits using complementary GaAs Heterojunction Field Effect Transistors(HFETs). Several operational amplifiers have been designed and their performance studied via simulation. The designs studied predict superior high frequency performance for C-HFETs over conventional GaAs MESFET and Silicon CMOS technology. The opamp designs are currently being implemented at Oregon State University for fabrication in the future. / Graduation date: 1993