Field-programmable analog arrays (FPAA) are integrated circuits with a collection of analog building blocks connected through a wire and switch fabric to achieve reconfigurability similar to the FPGAs of the digital domain. Like FPGAs, FPAAs can help reduce the time and money costs of the integrated circuit design cycle and make analog design much easier. In recent years, several types of FPAAs have been developed. Among these, FPAAs that use floating-gate transistors as programming elements have shown great potential in scalability because of the simplicity they provide in configuring the chip. Existing tools for programming FPAAs tend to be device specific and aimed at specific tasks such as filter design. To move FPAAs to the next step, more powerful and generic placement and routing tools are necessary. This thesis presents a placement and routing tool for large-scale floating-gate-based FPAAs. A topology independent routing resource graph (RRG) was used to model the FPAA routing topology, which enables generic description of any FPAA architecture with arbitrary connectivity including possible FPGA support in the future as well. So far, different FPAA architectures have been specified and routed successfully. The tool is already in use in classes and workshops for analog circuit and system design. Efficient ways to describe circuits and user constraints were developed to allow easy integration with other tools. Analog circuit performance was optimized by taking into account the routing parasitic effects on interconnects under various device-related constraints. Parasitic modeling allows simulation and evaluation of circuits routed on FPAA. Finally, a methodology was developed to explore the optimum architecture for a set of circuit classes by evaluating the efficiency of different architectures for each circuit class.

Translinear circuits are circuits in which the exponential relationship between the output current and input voltage of a circuit element is exploited to realize various algebraic or differential equations. This thesis is concerned with a subclass of translinear circuits, in which the basic translinear element, called a multiple-input translinear element (MITE), has an output current that is exponentially related to a weighted sum of its input voltages. MITE networks can be used for the implementation of the same class of functions as traditional translinear circuits. The implementation of algebraic or (algebraic) differential equations using MITEs can be reduced to the implementation of the product-of-power-law (POPL) relationships, in which an output is given by the product of inputs raised to different powers. Hence, the synthesis of POPL relationships, and their optimization with respect to the relevant cost functions, is very important in the theory of MITE networks. In this thesis, different constraints on the topology of POPL networks that result in desirable system behavior are explored and different methods of synthesis, subject to these constraints, are developed. The constraints are usually conditions on certain matrices of the network, which characterize the weights in the relevant MITEs. Some of these constraints are related to the uniqueness of the operating point of the network and the stability of the network. Conditions that satisfy these constraints are developed in this work. The cost functions to be minimized are the number of MITEs and the number of input gates in each MITE. A complete solution to POPL network synthesis is presented here that minimizes the number of MITEs first and then minimizes the number of input gates to each MITE. A procedure for synthesizing POPL relationships optimally when the number of gates is minimal, i.e., 2, has also been developed here for the single--output case. A MITE structure that produces the maximum number of functions with minimal reconfigurability is developed for use in MITE field--programmable analog arrays. The extension of these constraints to the synthesis of linear filters is also explored, the constraint here being that the filter network should have a unique operating point in the presence of nonidealities. Synthesis examples presented here include nonlinear functions like the arctangent and the gaussian function which find application in analog implementations of particle filters. Synthesis of dynamical systems is presented here using the examples of a Lorenz system and a sinusoidal oscillator. The procedures developed here provide a structured way to automate the synthesis of nonlinear algebraic functions and differential equations using MITEs.

Orientador: José Antonio Siqueira Dias / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-22T02:05:02Z (GMT). No. of bitstreams: 1 Guimaraes_HomeroLuz_D.pdf: 8320554 bytes, checksum: cbec86ea8c9ee3ad275baa5f37860192 (MD5) Previous issue date: 2013 / Resumo: Os experimentos em Física de alta energia tem se beneficiado enormemente do progresso alcançado na área de Microeletrônica, pois isto tem proporcionado a criação de detectores mais acurados e circuitos de processamento de sinais analógico/digitais cada vez mais rápidos e precisos. A redução no comprimento mínimo de canal dos processos CMOS além de proporcionar maior velocidade e precisão também reduz a área usada por cada canal, o que permite a implementação de mais canais numa mesma pastilha. Com um numero maior de canais por pastilha, com um mesmo numero de chips podemos programar um numero maior de canais do que anteriormente possível e com isso os físicos podem realizar uma reconstrução da trajetória de maneira mais precisa. Este Trabalho descreve uma proposta para o Trigger de nível zero baseando-se nas especificações disponíveis do Experimento Dzero no Fermi National Accelerator Laboraty (FERMILAB). Este trabalho descreve o projeto e implementação de um front-end analógico que detecta a carga provida pelo VLPC (detector luminoso usado no Dzero) seguida por um comparador de alta velocidade que fornece um nível lógico para um processador digital. O processador digital por sua vez usa uma arquitetura de processadores paralelos que, comunicando-se entre si são capazes de estimar a trajetória de partículas baseando-se em dados inicias programados a partir de simulações do detector feitas em computadores pelos Físicos. Tanto o bloco analógico quanto o processador digital foram implementados usando-se o processo CMOS90 da IBM / Abstract: The experiments in high-energy physics has benefited greatly from the progress made in the area of Microelectronics, since it has provided the creation of more accurate detectors and analog / digital signal processing circuits that are increasingly fast and accurate. The reduction in the minimum length of the channel in modern CMOS processes while providing greater speed and precision also reduces the area used by each channel, which enables the implementation of more channels on the same chip. With a larger number of channels per chip, we can with the same number of chips implement a larger number of channels than previously possible and with that physicists can perform a reconstruction of the trajectory more accurately. This work describes a proposal for a Trigger level zero based on the available specifications of the DZero experiment at the Fermi National Accelerator Laboraty (FERMILAB). In the following pages the design and implementation of an analog front-end that detects the charge provided by the VLPC detector followed by a high-speed comparator that provides a logical level to a digital processor are described. The digital processor in turn uses an architecture of parallel processors that communicate with each other are able in order to estimate the trajectory of particles based on initial data loaded in RAM based on simulations of the detector geometry made by physicists. Both the analog block and the digital processor are implemented using the IBM CMOS90 process / Doutorado / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

The performance of analog integrated circuits is dependent on the technology. Digital circuits are scalable in nature, and the same circuit can be scaled from one technology to another with improved performance. But, in analog integrated circuits, the circuit components must be re-designed to maintain the desired performance across different technologies. Moreover, in the case of digital circuits, minimum feature-size (short channel length) devices can be used for better performance, but analog circuits are still being designed using channel lengths larger than the minimum feature sizes. The research in this thesis is aimed at understanding the impact of technology scaling and short channel length devices on the performance of analog integrated circuits. The operational amplifier (op amp) is chosen as an example circuit for investigation. The performance of the conventional op amps are studied across different technologies for short channel lengths, and techniques to develop technology-independent op amp architectures have been proposed. In this research, three op amp architectures have been developed whose performance is relatively independent of the technology and the channel length. They are made scalable, and the same op amp circuits are scaled from a 0.25 um CMOS onto a 0.18 um CMOS technology with the same components. They are designed to achieve large small-signal gain, constant unity gain-bandwidth frequency and constant phase margin. They are also designed with short channel length transistors. Current feedback, gm-boosted, CMOS source followers are also developed, and they are used in the buffered versions of these op amps.