Static Random Access Memory (SRAM) is a critical component in mobile video processing systems. Because of the large video data size, the memory is frequently accessed, which dominates the power consumption and limits battery life. In energy-efficient SRAM design, a substantial amount of research is presented to discuss the mechanisms of approximate storage, but the content and environment adaptations were never a part of the consideration in memory design. This dissertation focuses on optimization methods for the SRAM system, specifically addressing three areas of Intelligent Energy-Efficient Storage system design. First, the SRAM stability is discussed. The relationships among supply voltage, SRAM transistor sizes, and SRAM failure rate are derived in this section. The result of this study is applied to all of the later work. Second, intelligent voltage scaling techniques are detailed. This method utilizes the conventional voltage scaling technique by integrating self-correction and sizing techniques. Third, intelligent bit-truncation techniques are developed. Viewing environment and video content characteristics are considered in the memory design. The performance of all designed SRAMs are compared to published literature and are proven to have improvement.

The low power regime has attracted various researchers in the information theory and communication communities to understand the performance limits of wireless systems. Indeed, the energy consumption is becoming one of the major limiting factors in wireless systems. As such, energy-efficient wireless systems are of major importance to the next generation wireless systems designers. The capacity is a metric that measures the performance limit of a wireless system. The study of the ergodic capacity of some fading channels in the low power regime is the main subject of this thesis. In our study, we consider that the receiver has always a full knowledge of the channel state information. However, we assume that the transmitter has possibly imperfect knowledge of the channel state information, i.e. he knows either perfectly the channel or only an estimated version of the channel. Both radio frequency and free space optical communication channel models are considered. The main contribution of this work is the explicit characterization of how the capacity scales as function of the signal-to-noise ratio in the low power regime. This allows us to characterize the gain due to the perfect knowledge compared to no knowledge of the channel state information at the transmitter. In particular, we show that the gain increases logarithmically for radio frequency communication. However, the gain increases as log2(Pavg) or log4(Pavg) for free-space optical communication, where Pavg is the average power constraint imposed to the input. Furthermore, we characterize the capacity of cascaded fading channels and we applied the result to Rayleigh-product fading channel and to a free-space optical link over gamma-gamma atmospheric turbulence in the presence of pointing errors. Finally, we study the capacity of Nakagami-m fading channel under quality of service constraints, namely the effective capacity. We have shown that the effective capacity converges to Shannon capacity in the very low power regime.

Current cancer therapies are highly cytotoxic and their delivery to exclusively the affected site is poorly controlled, resulting in unavoidable and often severe side effects. In an effort to overcome such issues, magnetic nanoparticles have been recently gaining relevance in the areas of biomedical applications and therapeutics, opening pathways to alternative methods. This led to the concept of magnetic particle hyperthermia in which magnetic nano beads are heated by a high power magnetic field. The increase in temperature kills the cancer cells, which are more susceptible to heat in comparison to healthy cells. In this dissertation, the possibility to kill cancer cells with magnetic nanowires is evaluated. The idea is to exploit a magnetomechanical effect, where nanowires cause cancer cell death through vibrating in a low power magnetic field. Specifically, the magnetic nanowires effects to cells in culture and their ability to induce cancer cell death, when combined with an alternating magnetic field, was investigated. Nickel and iron nanowires of 35 nm diameter and 1 to 5 μm long were synthesized by electrodeposition into nanoporous alumina templates, which were prepared using a two-step anodization process on highly pure aluminum substrates. For the cytotoxicity studies, the nanowires were added to cancer cells in culture, varying the incubation time and the concentration. The cell-nanowire interaction was thoroughly studied at the cellular level (mitochondrial metabolic activity, cell membrane integrity and, apoptosis/necrosis assay), and optical level (transmission electron and confocal microscopy). Furthermore, to investigate their therapeutic potential, an alternating magnetic field was applied varying its intensity and frequency. After the magnetic field application, cells health was measured at the mitochondrial activity level. Cytotoxicity results shed light onto the cellular tolerance to the nanowires, which helped in establishing the appropriate nanowire concentrations to use the nanowires + alternating magnetic field combination as a cancer treatment. Different levels of cancer cell death were achieved by changing the incubation time of the nanowires with the cells and the alternating magnetic field parameters. Cell viability was significantly affected in terms of mitochondrial activity and cell membrane integrity after applying the treatment (nanowires + alternating magnetic field) using a low-frequency alternating magnetic. Theoretical calculations considering the magnetic and viscous torques showed that the nanowires vibrate as a consequence of the applied magnetic field. This, alongside the fact that no temperature increase was measured during the treatment, makes the magnetomechanical effect the most probable action mechanism in the applied treatment that is inducing cell death. Inducing cancer cell death via magnetomechanical action using magnetic nanowires resulted in killing up to 60% of cancer cells with only 10 minutes of treatment. The required magnetic field for treatment is in a low power regime, which is safe, does not cause any discomfort to the patients, and can be generated with compact and cheap instruments.

Convolutinal coding is a coding scheme often employed in deep space communications and recently in digital wireless communications. Viterbi decoders are used to decode convolutional codes. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. With the proliferation of battery powered devices such as cellular phones and laptop computers, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of Viterbi decoders for wireless communications applications. In CMOS technology the major source of power dissipation is attributed to dynamic power dissipation, which is due to the switching of signal values. The focus of our research in the low-power design of Viterbi decoders is reduction of dynamic power dissipation at logic level in the standard cell design environment. We considered two methods, clock-gating and toggle-filtering, in our design. A Viterbi decoder consists of five blocks. The clock-gating was applied to the survivor path storage block and the toggle-filtering to the trace-back block of a Viterbi decoder. We followed the standard cell design approach to implement the design. The behavior of a Viterbi decoder was described in VHDL, and then the VHDL description was modified to embed the low-power design. A gate level circuit was obtained from the behavioral description through logic synthesis, and a full scan design was incorporated into the gate level circuit to ease testing. The gate level circuit was placed and routed to generate a layout of the design. Our experimental result shows the proposed design reduces the power dissipation of a Viterbi decoder by about 42 percent compared with the on without considering the low-power design. / Master of Science

Indiana University-Purdue University Indianapolis (IUPUI) / With the growing popularity and use of devices under the great umbrella that is the Internet of Things (IoT), the need for devices that are smaller, faster, cheaper and require less power is at an all time high with no intentions of slowing down. This is why many current research efforts are very focused on energy harvesting. Energy harvesting is the process of storing energy from external and ambient sources and delivering a small amount of power to low power IoT devices such as wireless sensors or wearable electronics. A charge pumps is a circuit used to convert a power supply to a higher or lower voltage depending on the specific application. Charge pumps are generally seen in memory design as a verity of power supplies are required for the newer memory technologies. Charge pumps can be also be designed for low voltage operation and can convert a smaller energy harvesting voltage level output to one that may be needed for the IoT device to operate. In this work, an integrated FinFET (Field Effect Transistor) charge pump for low power energy harvesting applications is proposed. The design and analysis of this system was conducted using Cadence Virtuoso Schematic L-Editing, Analog Design Environment and Spectre Circuit Simulator tools using the 7nm FinFETs from the ASAP7 7nm PDK. The research conducted here takes advantage of some inherent characteristics that are present in FinFET technologies, including low body effects, and faster switching speeds, lower threshold voltage and lower power consumption. The lower threshold voltage of the FinFET is key to get great performance at lower supply voltages. The charge pump in this work is designed to pump a 150mV power supply, generated from an energy harvester, to a regulated 650mV, while supplying 1uA of load current, with a 20mV voltage ripple in steady state (SS) operation. At these conditions, the systems power consumption is 4.85uW and is 31.76% efficient. Under no loading conditions, the charge pump reaches SS operation in 50us, giving it the fastest rise time of the compared state of the art efforts mentioned in this work. The minimum power supply voltage for the system to function is 93mV where it gives a regulated output voltage of $25mV. FinFET technology continues to be a very popular design choice and even though it has been in production since Intel's Ivy-Bridge processor in 2012, it seems that very few efforts have been made to use the advantages of FinFETs for charge pump design. This work shows though simulation that FinFET charge pumps can match the performance of charge pumps implemented in other technologies and should be considered for low power designs such as energy harvesting.

No description available.

<p> In past years, wireless technology has seen an incredible boom. As a result, industry has gone to great lengths to make wireless devices cheaper, smaller, faster and less power- hungry. This has prompted a significant interest in the research world to design circuit components that would facilititate these goals. However, much of the focus has been on wireless technology for communications applications, such as wireless telephony and wireless computer networking. More recently, there has been a focus on developing circuits for other wireless applications, one of which is wireless sensor networks. Such applications would demand extremely low-power operation, especially from the RF front-end. We have concentrated on achieving low-power operation for one of the important building blocks of the RF transceiver, which is the frequency downconversion mixer. </p> <p> In this thesis, we describe the design and results of two mixers, both designed in CMOS O.l8J.Lm technology offered by the Canadian Microelectronics Corporation (CMC). The first design uses the body terminal of the transistor as one of the inputs. This method allows for the radio-frequency (RF) and local oscillator (LO) stages in traditional switching mixers to be collapsed into one stage, thereby allowing for operation at lower supply voltages and lower power comsumption levels. This mixer was designed to downconvert a 1.9GHz RF signal to a 250MHz intermediate-frequency (IF) signal. The measured performance characteristics resulted in a power consumption of 400J.LW from a 0.8V supply, a conversion gain of 1dB, a single sideband (SSB) noise figure of 1ldB, and an input-referred 3rd-order intercept point (IIP3) of -9dBm. </p> <p> The second mixer design used a folding architecture to reduce the supply voltage headroom needed, as well as distribute the current appropriately for high-gain and lowpower operation. This mixer was designed to downconvert a 2.4GHz RF signal to a 100MHz IF signal. The simulated performance characteristics showed a power consumption of 640).1 W from a 1 V supply, a conversion gain of 4dB, a SSB noise figure of 19dB, and an IIP3 of -6.5dBm. </p> / Thesis / Master of Applied Science (MASc)

Trustworthy authentication of an object is of extreme importance for secure protocols. Traditional methods of storing the identity of an object using non-volatile memory is insecure. Novel chip-identifiers called Silicon Physical Unclonable Functions (PUFs) extract the random process characteristics of an Integrated Circuit to establish the identity. Though such types of IC identifiers are difficult to clone and provide a secure, yet an area and power efficient authentication mechanism, they suffer from instability due to variations in environmental conditions and noise. The decreased stability imposes a penalty on the area of the PUF circuit and the corresponding error correcting hardware, when trying to generate error-free bits using a PUF. In this thesis, we propose techniques to improve the popular delay-based PUF architectures holistically, with a focus on its stability. In the first part, we investigate the effectiveness of circuit-level optimizations of the delay based PUF architectures. We show that PUFs which operate in the subthreshold region, where the transistor supply voltage is maintained below the threshold voltage of CMOS, are inherently more stable than PUFs operating at nominal voltage because of the increased difference in characteristics of transistors at this region. Also, we show that subthreshold PUF enjoys higher energy and area efficiency. In the second part of the thesis, we propose a feedback-based supply voltage control mechanism and a corresponding architecture to improve the stability of delay-based PUFs against variations in temperature. / Master of Science

Wireless video systems have applications in cellular videophones, surveillance systems, and mobile patrols. The design of a wireless video system must consider two important constraints: low bit rate and low power dissipation. The ITU-T H.263 video codec standard is suitable for low bit rate wireless video systems, however it is computationally intensive. Some of the most computationally intensive operations in H.263 are the Discrete Cosine Transform (DCT) and the Inverse Discrete Cosine Transform (IDCT), which perform spatial compression and decompression of the data. In an ASIC implementation of H.263, the high computational complexity of the DCT and IDCT leads to high power dissipation of the blocks. Low power design of the DCT and IDCT is essential in a portable wireless video system. This paper examines low power design techniques for DCT and IDCT circuits applicable for low bit rate wireless video systems. Five low power techniques are applied to baseline reference DCT and IDCT circuits. The techniques include skipping low energy DCT input, skipping all-zero IDCT input, low precision constant multipliers, clock gating, and a low transition data path. Gate-level simulations characterize the effectiveness of each technique. The combination of all techniques reduces average power dissipation by 95% over the baseline reference DCT and IDCT blocks. / Master of Science

The growing demand of “System on a Chip” applications necessitates integration of multiple devices on the same chip. Analog to Digital conversion is essential to interfacing digital systems to external devices such as sensors. This presents a difficulty since high precision analog devices do not mix well with high speed digital circuits. The digital environment constraints put demand on the analog portion to be resource efficient and noise tolerant at the same time. Even more demanding, Analog to Digital converters must consume a small amount of power since “System on a Chip” circuits often target portable applications. Analog to digital conversion based on Delta Sigma modulation offers an optimal solution to the above problems. It is based on digital signal processing theory and offers benefits such as small footprint, high precision, noise de-sensitivity, and low power consumption. This thesis presents a methodology for designing low power Delta Sigma modulators using a combination of modern circuit design techniques. The developed techniques have resulted in several modulators that satisfy the initial design parameters. We applied this method to design three different modulators in the 0.35um digital CMOS technology with a 3.3V supply voltage. A first order Self-Referenced modulator has a resolution of 8 bits and the lowest power consumption at 75 uW. The most successful design is the second order Self Referenced modulator that produces 12 bits of resolution with a power consumption of 87 uW. A second order Floating Gate modulator possesses features for high noise rejection, and produces 10 bits of resolution while consuming 276 uW. It is concluded that self-referenced modulators dissipate less power and offer higher performance as compared more complicated circuits such as the floating gate modulator. / Master of Science