Continuous-time sigma-delta modulator can be applied to wireless communications, photography and MP3 player. Portable electronics products became mainstream the design of a low power consumption analog circuit become important. Therefore, this paper presents a low power consumption continuous-time sigma-delta modulator. The low-power continuous-time sigma-delta modulator includes one-bit quantizer and a third-order loop filter consisting of resistor-capacitor integrators. Through the modified Z-transform, the discrete time loop filter design is transformed to the continuous time loop filter design. The proposed sigma-delta modulator used TSMC 0.18£gm CMOS 1P6M standard process, and its supply voltage is 1V, oversampling ratio is 32, bandwidth is 200 KHz, effective number is 13bit, power consumption is 1.5mW. Keywords: GSM, low power consumption, low power supply, continuous-time, sigma-delta modulator.

In spite of the fast development of the medical sector, cardiovascular diseases are still the major cause of death in the world. The identification of the patient who presents a risk situation that may result in death is still a challenge. The number of systems to monitor vital signs has increased in the last years, with more compact devices, and a range of parameters that help the medical team to monitor the development of the patients\' clinical situation. This work presents the modeling and development of a low-power portable ECG to be used as input of the system to monitor cardiac signals, generated in PROCADNF-1493/2007. The aim of this device is to promote a communication with a computer enabling the analysis of the ECG signal using a software for research in this area. It was used a wireless communication system using the Zigbee technology with the band of 2.4GHz and a range of approximately 70 meters without a wall. This promotes the analysis of the ECG in movement, in which the patient has the possibility to move. To support the construction of such system, this work presents an architecture review, a state-of-the-art in hardware, as well as a study and a model specification of a low-power portable ECG used to aid the research that aim the monitoring of vital signs. Finally, a qualitative analysis of the constructed hardware is provided. / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Apesar do rápido desenvolvimento da medicina, as doenças cardiovasculares ainda são uma das principais causa de morte no mundo. A identificação do paciente que apresenta um quadro de risco que pode decorrer a morte súbita é ainda um desafio. Os sistemas de monitoramento de sinais vitais vêm crescendo nos últimos anos, com aparelhos cada vez mais compactos, e uma gama de parâmetros que auxiliam a equipe médica a acompanhar o desenvolvimento do quadro clínico de seus pacientes. Este trabalho apresenta o modelo e o desenvolvimento de um Eletrocardiógrafo portátil, de baixo consumo para ser usado como entrada do sistema de monitoração dos sinais cardíacos, gerado no PROCAD NF-1493/2007. O objetivo desse aparelho é de promover a comunicação com o computador, possibilitando a análise do sinal do eletrocardiograma através de softwares desenvolvidos para pesquisas nesta área. Trabalhou-se neste projeto com um sistema de comunicação sem o utilizando a tecnologia Zigbee com a faixa de comunicação de 2,4GHz, e um alcance de aproximadamente 70 metros sem barreira, Isso favorece a análise do sinal ECG com o paciente em locomoção. Para embasar a construção do referido sistema, o presente trabalho apresenta uma revisão de arquiteturas, estado da arte, em hardware, bem como um estudo e uma especificação do modelo de um ECG portátil de baixa potência, usado neste trabalho para auxiliar as pesquisas voltadas a monitoração de sinais vitais. Por fim, uma análise qualitativa do hardware construído é fornecida.

Depuis les 20 dernières années, l'essor de l'IoT et du "cloud computing" a conditionné le besoin dedéployer massivement, et globalement, des capteurs afin d'alimenter des bases de données et améliorerla précision des algorithmes d'analyse. Pour répondre à ces demandes, de nouveaux réseaux basés surles bandes de fréquences ISM ont été déployés. Nous avons donc appréhendé de façon complète cestechnologies afin de garantir une qualité maximale pour nos produits mais aussi proposer des conseilsjustes dans un secteur ou abus de langage et promesses de performances sont monnaie courante.Cependant, le nombre grandissant d'objets émettant sous la fréquence du gigahertz lève un doutequant à l'impact sur la santé des êtres vivants. Dès lors, coupler l'aspect non invasif des VLC avecl'Internet des Objets permettrait non seulement de réduire les risques pour les êtres humains maisaussi de limiter la saturation des bandes radio.Néanmoins, les techniques d'aujourd'hui consistent principalement en la réalisation de systèmesdiffusant l'information depuis une source unique vers plusieurs récepteurs, ce qui est l'inverse du paradigmede l'IoT. Dans cette étude, nous avons donc réalisé un nouveau design basé sur les VLC qui meten place une topologie de réseau en étoile 3. Ce système, basé sur un concentrateur disposant d'une ouplusieurs caméra en guise de photo-récepteurs, est optimisé pour plus d'autonomie. Ainsi, la vitessede transmission peut être gérée dynamiquement sans être connue par les autres éléments du système. / In the last 20 years, the coming up of Internet of Things and Cloud Computing has conditionedthe need to deploy sensors everywhere to feed databases and analytics. To meet this requirements,new kind of networks have been massively deployed based on the sub-gigahertz frequency which haveunknown effect on human health.Couple the non-invasive aspect of the Visible Light Communication (VLC) with IoT could notonly reduce potential risks for human health but also avoid radio band saturation. However, today'stechniques consist mainly in broadcast data from light sources to receivers which is the opposite of theIoT paradigm. In this study, we will present a new design where the gateway is not a classic photodiodebut a camera.With this camera based method, we are able to design a star network using VLC. Even if the datarate is not the same as standard method, we are now able to collect data emanating from many sensorsat once with only one photoreceptor. This system also includes the ability of discriminate LED matrix,which transfer the same data faster, and single LED. Finally, data rate can be handle autonomouslyby the system to provide an optimal data transfer.

Power consumption is gradually becoming an important issue of designing computing systems. Most of the researches of low power issues have focused on semiconductor techniques or hardware architecture designs, but less utilized the techniques of software optimization. This paper presents a new scheduling methodology in source code level for Intelligent Memory System, which reduces the energy consumption by means of code compilation techniques. The scheduling kernel provides two options for users: performance-oriented low power scheduling and energy-oriented low power scheduling, to achieve the objective of considering high performance and low power issues. The experimental results are also presented and discussed.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The Instrumentation and Telemetry Departments at Sandia National Laboratories have been exploring the instrumentation of sealed canisters where the flight application will not tolerate either the presence of a chemical power source or penetration by power supply wires. This paper will describe the application of a low power micro-controller based instrumentation system that uses magnetic coupling for both power and data to support a flight application.

The main design requirements for today's mobile applications are: · high throughput performance. · high energy efficiency. · high programmability. Until now, the choice of platform has often been limited to Application-Specific Integrated Circuits (ASICs), due to their best-of-breed performance and power consumption. The economies of scale possible with these high-volume markets have traditionally been able to hide the high Non-Recurring Engineering (NRE) costs required for designing and fabricating new ASICs. However, with the NREs and design time escalating with each generation of mobile applications, this practice may be reaching its limit. Designers today are looking at programmable solutions, so that they can respond more rapidly to changes in the market and spread costs over several generations of mobile applications. However, there have been few feasible alternatives to ASICs: Digital Signals Processors (DSPs) and microprocessors cannot meet the throughput requirements, whereas Field-Programmable Gate Arrays (FPGAs) require too much area and power. Coarse-grained dynamically reconfigurable architectures offer better solutions for high throughput applications, when power and area considerations are taken into account. One promising example is the Reconfigurable Instruction Cell Array (RICA). RICA consists of an array of cells with an interconnect that can be dynamically reconfigured on every cycle. This allows quite complex datapaths to be rendered onto the fabric and executed in a single configuration - making these architectures particularly suitable to stream processing. Furthermore, RICA can be programmed from C, making it a good fit with existing design methodologies. However the RICA architecture has a drawback: poor scalability in terms of area and power. As the core gets bigger, the number of sequential elements in the array must be increased significantly to maintain the ability to achieve high throughputs through pipelining. As a result, a larger clock tree is required to synchronise the increased number of sequential elements. The clock tree therefore takes up a larger percentage of the area and power consumption of the core. This thesis presents a novel Dynamically Reconfigurable Asynchronous Processor (DRAP), aimed at high-throughput mobile applications. DRAP is based on the RICA architecture, but uses asynchronous design techniques - methods of designing digital systems without clocks. The absence of a global clock signal makes DRAP more scalable in terms of power and area overhead than its synchronous counterpart. The DRAP architecture maintains most of the benefits of custom asynchronous design, whilst also providing programmability via conventional high-level languages. Results show that the DRAP processor delivers considerably lower power consumption when compared to a market-leading Very Long Instruction Word (VLIW) processor and a low-power ARM processor. For example, DRAP resulted in a reduction in power consumption of 20 times compared to the ARM7 processor, and 29 times compared to the TIC64x VLIW, when running the same benchmark capped to the same throughput and for the same process technology (0.13μm). When compared to an equivalent RICA design, DRAP was up to 22% larger than RICA but resulted in a power reduction of up to 1.9 times. It was also capable of achieving up to 2.8 times higher throughputs than RICA for the same benchmarks.

This study contributes to the domain of application specific adaptive hardware architectures with a design approach on processing element array, interconnect structure and memory interface concurrently. As summarized below, our architectural design choices push the limits of on-chip data reuse and avoid redundant computations that are essential for the high throughput, small area, and low power demands of the consumer market.Motion estimation (ME) is a key component in the H.264/AVC standard. Full Search (FS) based ME achieves optimal peak signal-to-noise-ratio (PSNR), and is the most adopted algorithm for developing hardware motion estimators. In this study, we first design a variable block size motion estimation (VBSME) engine based on hybrid grained processing elements (PEs) and a 2D programmable interconnect structure, which is adaptive to all block size configurations of H.264. PEs operate in bit-serial manner using MSB-first arithmetic for early termination to reduce the amount of computations, and the 2D architecture enables on-chip data reuse between neighboring PEs in a bit-by-bit pipelined fashion. Our design reduces the gate count by 7x compared to its ASIC counterpart, operates at a comparable frequency while sustaining 30 and 60 frames per second (fps); and outperforms bit parallel and bit serial architectures in terms of throughput and performance per gate.Numerous fast search algorithms (diamond, hexagon, three-step, etc.) have been developed to reduce the computation burden and the excessive amount of memory transactions required by FS, with a compromise in compression quality. We improve our VBSME engine and introduce the first adaptive ME architecture that provides the end user with the flexibility of choosing between the high quality video service during power-rich state (FS mode), and extended video service (fast search mode). We resolve the irregular indexing scheme challenge of three-step search (3SS) by introducing an on-chip buffer structure with a memory interface, which is adaptive to data access patterns of the FS and 3SS methods. The architecture sustains the real time CIF format (352x288) video encoding at 30fps with an operational frequency as low as 17.6MHz, and consumes 1.98mW based on the 45nm technology, outperforming all other FS and 3SS architectures.

Non traduit / The introduction of nanometer technologies, has allowed the semiconductor industry to create nanoscale devices in combination with gigascale complexity. However, new technologies bring with them new challenges. In the era of large systems embedded in a single System-On-Chip and fabricated in continuously shrinking technologies, it is important to test and ensure fault-free operation of the whole system. The cost involved in semiconductor test has been steadily growing and testing techniques for integrated circuits are today facing many exciting and complex challenges. Although important advances have been made, existing test solutions are still unable to exhaustively cover all types of defects in advanced technology nodes. Consequently, innovative solutions are required to cope with new failure mechanisms under the constraints of higher density and complexity, cost and time to market pressure, product quality level and usage of low cost test equipment.The work of this thesis is focused on the development of silicon test and characterization methodologies that aid in the accurate detection and resolution of issues that may arise due to variability, manufacturing defects, wear-out or interference. A wide spectrum of these challenges has been addressed from a test perspective to ensure that the availability of effective test solutions does not become a bottleneck in the path towards further scaling. Additionally the advances and innovations introduced in the myriad domains of electronic design, reliability management, manufacturing process improvements etc. that call for the development of advanced, modular and agile test methodologies have been effectively covered within the scope of this work.This thesis presents the significant contributions made for enabling resolution of state of the art industrial test challenges via the design and implementation of novel test strategies (targeting the 28nm FDSOI technology node) for:•Detection & diagnosis of timing faults in standard cells.•Analysis of Setup and Hold margins within silicon.•Verification & reliability analysis of innovative test structures.•Analysis of on-chip self heating.•Enabling characterization and performance evaluation of high speed digital IPs.

This thesis documents the design and analysis of a low-power integrated ultra-wideband (UWB) receiver that is well suited for usage in medium to low rate, location aware communication systems. For the first time, this receiver design explores and exploits the unique properties of UWB pulse technology. By exploiting low emission power limit and pulse based communication, RF circuits have been designed with reduced linearity to achieve low-power operation and better circuit performance. The receiver design in this thesis follows a top-down approach which begins by focusing on UWB-specific issues such as signal characteristics, modulation schemes, potential advantages, and design challenges. Next, different receiver architectures are evaluated in terms of their circuit complexity, power consumption, and levels of integration. The impact of various analog non-idealities on the performance of UWB systems is also analysed in detail. After evaluating the performance of UWB systems operating with non-linear frontends, the use of pulse doublets is introduced, for the first time, to mitigate nonlinearityinduced distortion. Simulation results demonstrate that under non-linear operating conditions, significant BER improvements can be achieved by using filtering, pulse doublet, and direct sequence spread spectrum techniques. When ADC quantization effects are included in the receiver, analysis shows that quantization noise dominates distortion-induced BER degradation when two or three bits ADCs are employed. Consequently, reduced front-end linearity requirements can be tolerated in exchange for improvements in the more critical circuit parameters of the UWB receiver. By adopting the sub-linear circuit design approach, a direct-conversion receiver prototype is implemented in the 0.5 um SOS CMOS technology according to specifications determined from system-level Simulink simulations. This highly integrated receiver prototype contains a low-noise amplifier, a 4-GHz frequency synthesizer, mixers, baseband amplifiers and filters, and 2-GSps two-bit analog-to-digital converters. The receiver prototype consumes 75-mW of power, the lowest amount for reported UWB receivers operating in the 3.1 to 10.6-GHz band. Complete end-to-end simulations of the system are performed in Simulink, revealing an achievable BER of approximately 8x10e-4 Finally, a novel 79-uW 5.6-GHz CMOS frequency divider with on-chip temperature and processing compensation have been designed. The divider, designed in a 0.25 um SOS-CMOS technology, occupies 35 x 25 um2 and achieves an operating frequency of 5.6-GHz while consuming 79-uW at a supply voltage of 0.8V. The power efficiency of 143-GHz/mW is one of the highest achieved among conventional CMOS dividers. When combined with a simple and effective compensation submodule, the proposed divider is shown to achieve process and temperature-insensitive operation in a 5-GHz UNII band frequency synthesizer.

<p>In wireless communication there is commonly much unnecessary communication made in directions not pointing towards the recipient. Normally omni directional antennas are being used which sends the same amount of energy in all directions equally. This waste of energy reduces the lifetime of battery powered units and causes more traffic collisions than necessary. One way of minimizing this wasted energy and traffic collisions, is to use another type of antenna called “smart antenna”. These antennas can use selectable radiation patterns depending on the situation and thus drastically minimize the unnecessary energy waste. Smart antennas also provide the ability to sense the direction of incoming signals which is favorable for physical layout mapping such as orientation.</p><p>This thesis presents the prototyping of a new type of smart antenna called the SPIDA smart antenna. This antenna is a cheap to produce smart antenna designed for the 2.4 GHz frequency band. The SPIDA smart antenna can use sixty-four different signal patterns with the control of six separate directional modes, amongst these patterns are six single direction patterns, an omni-directional signal pattern and fifty-six combi-direction patterns. The thesis presents complete building instructions, evaluation data and functional drivers for the SPIDA smart antenna.</p>