Because IC (Integrated Circuit) has some good features like: little, low power consumption, and high stable, so it already popularly applied to our daily life. Operation is one of the main functions of IC, and now operate function achieve in digital mode of many IC products. Although digital circuits have many advantages, but we live in the analog world, natural signals are all analog. Digital circuits can¡¦t direct process analog signals, and therefore we have a requirement of analog-to-digital converter. As time goes by, IC technology has made great progress; digital circuits have faster process ability, and we also require a high speed analog-to-digital converter. Besides, in order to achieve higher picture quality and clearer voice, we also require a high resolution analog-to-digital converter. For portable products, the power consumption also needs to take into account. As mentioned above, I will implement a high speed, high resolution and low power analog-to-digital converter. In this thesis, the circuits are designing with TSMC.18£gm 1P6M CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100Ms/s and 12bits individually. The pipelined coupling with 1.5bit/stage constitutes the main architecture of analog-to-digital converter. The dynamic comparator is used for lower power. Finally, the output codes are translated by digital correction circuit. Keywords: ADC, Analog-to-Digital Converter, pipeline, low power, amplifier, comparator.

In today¡¦s modern society, our latest up-to-date technology contains various types of multimedia applications. These applications don¡¦t necessarily have to be executed with the most precise accuracy. In short, they are fault tolerant. As a consequence, this thesis proposes a multi-precision iterative floating-point special function unit, which can be executed under different modes to meet the error requirements of each specific application, and also achieve power reduction during the process. In order to minimize the area of our design, we have developed two iterative architectures to implement the multi-precision floating point special function unit. The first proposed architecture can perform three kinds of operations, which include a reciprocal operation, a reciprocal square root operation, and last but not least, a logarithm operation. After deciding which function is to be performed, the user can choose four precision modes to execute the special function unit. According to each mode from lowest precision to highest, we name them the first mode, the second mode, the third mode, and the fourth mode. During implementation, a C model has also been designed to evaluate the maximum error of each mode by making comparisons with the most accurate software result, which is the 23 bit result. When the reciprocal function is chosen, and the user defines that application to be performed in full precision, the multi-precision special function operator needs to be executed twice, and it has the error rate of approximately 0.0001%. When less precision is required, we can choose from two intermediate modes, one offers 15 bit accuracy, and the other can guarantee a 12 bit precision. The former precision mode also required the hardware to be executed twice, but the latter only once. The 15 bit accuracy mode has an error rate around 0.01¢H, and the 12 bit mode has the error rate roughly around 0.05¢H. In addition, when visual effects or even audio effects are not our greatest concern, we provide a least accurate mode for the users to pick to execute the special function operator. This mode can maintain 8 bit accuracy, and has the error rate of approximately 0.8%. Other operations including the reciprocal square root, and the logarithm also have four precision modes to choose from. The reciprcocal square root operation can guarantee the same accuracy in each mode as the reciprocal operation, and their error rates are 0.004%, 0.01%, 0.06%, and 0.5% from the highest precision mode to the lowest one. The precisions the logarithm operation can guarantee from highest accuracy to the lowest one are 23, 16, 12, and 8 bits, respectively, and have error rates including 0.00003%, 0.002%, 0.06%, and 0.3%. These different precision choices are built in the proposed structure mainly to reduce the power consumption. The main concept is to pick a low precision mode in order shut down some components in our design. In addition to switching modes, we¡¦ve also added tri-state buffers in certain components as another means to decrease power. Through experimental results we¡¦ve discovered that the proposed architecture¡¦s affect on power reduction was not as we¡¦ve expected. Due to the integration of the Newton Raphson Method and the Piecewise Polynomial Approximation Method, our architecture¡¦s delay and area have largely increased, and causing a bad influence on saving power. As a consequence, we¡¥ve developed a second architecture to meet our demands. This architecture is mainly based on the Piecewise Polynomial Approximation Method. From this method, we¡¦ve implemented an iterative design which also supports three kinds of operations, the same as the first architecture. It also provides three precision modes for the user to choose. The lowest precision mode provides 8 bit accuracy. The second mode provides 14 bit accuracy, and the third mode, which is the most precise mode, can provide 22 bit accuracy. According to our C model, we can specify our maximum error rate in each function while executing under different modes. When the reciprocal function is executed, the largest error rate in from the lowest mode to the highest mode is 0.19%, 0.00006% and 0.000015% , and the error rate for reciprocal square root from lowest precision mode to the highest is 0.09%, 0.000022% and 0.000014%, and the error rate for the logarithm function is 0.33%, 0.000043% and 0.000015%, from the lowest to the highest. From experimental results we can discover that the newly proposed architecture is better in comparison with the traditional Piecewise Polynomial Approximation architecture. The proposed architecture has a smaller area, and a faster delay, and most important of all, it reduces power and energy affectively.

In wireless communication system, convolutional coding method is often used to encode the data. In decoding convolutional code (CC), Viterbi algorithm is considered to be the best mechanism. Viterbi decoder (VD) was developed to execute the algorithm on mobile devices more effectively. This decoder is often used on 2G and 3G mobile phones. However, on 2G phones, VD consumes about one third of total power consumption of the signal receiver. Therefore it is very necessary to reduce the power consumption of VD on 2G and 3G phones. VD uses large amount of register in survivor metric unit (SMU), so that the decoder can receive enough CC and converge automatically. The goal of this thesis is to decrease power consumption of SMU by using path metric compare unit (PMCU) to find the best state of path metric unit (PMU). This way decreases half of registers and multiplexers required in SMU, leading to significant area reduction in decoder. During the process of signal transmission in wireless communication, different causes like the atmosphere, outer space radiation and man-made will interfere the signal by different degree. The stronger the noise is, the more interference CC will get. The error detection circuit used will mark the sections with noise interference before the CC enters the VD. If CC is interfered, it will be decoded by the whole VD. Otherwise, it will be decoded by low power decoder, where the controller will start clock gating mechanism on SMU to close up unnecessary power consumption block. The power consumption of is varying proposed Adaptive Viterbi decoder according to the interference degree. When interference degree is high, the power consumption is 21% less than conventional VD; when interference is low, it is 44% less. The results show that the proposed method can effectively reduce the power consumption of VD.

Acquisition of bio-signals is an important feature in advanced medical applications. In order to record bio-signals such as electrocardiogram (ECG) or electromyogram (EMG), a switched-capacitor amplifier with variable linear gain and low noise front-end is discussed in this thesis. The circuit is designed and implemented as an Application-Specific Integrated Circuit (ASIC). This ASIC consists of transconductance stage with custom-designed lateral bipolar transistors in the input stage, switched-capacitor integrating stage, sample-and-hold circuit and buffer output stage. Lateral bipolar transistors were chosen with the intention of reducing flicker noise compared to using MOS input devices. Using a switched-capacitor (SC) stage the gain is adjustable to accommodate input signals of different amplitude making it useful for the recording of different biomedical signals. Adjustable gain is achieved by varying the clock phase delay between two digital control signals which were generated by a microcontroller. Also, small size and low supply voltage operation (¡Ó0.9 V) are achieved. Therefore, this ASIC may be used in wearable or even with implantable medical applications. Measured results for test chips realized in TSMC 0.35 £gm CMOS technology are reported confirming the correct operation of the circuit.

Home medical equipment becomes increasingly popular as VLSI fabrication technology advances. However, there are two important factors for realizing a miniaturized biochip: low noise [1] and low power. Firstly, physiological signals are very susceptible to interference while the amplitude of the signal is only a few millivolts or less. If the circuit cannot reject noise effectively, it is hard to amplify the signal and obtain the output voltage of the recording system accurately. Secondly, it is not convenient to replace the batteries frequently when using the portable measurement instrument for the patients. This thesis is focused on the measurement of physiological signals, such as electrocardiography (ECG) [2], electroneurogram (ENG) [3] and electromyography (EMG) [4] , and designing an all-in-one recording system to measure the different physiological signals in a chip. For this purpose, a programmable multi-parameter system for recording of the wide range of physiological signals is designed. The system provides two types of input transconductance stages, BiCMOS and CMOS. BiCMOS amplifiers provide high gain , low noise [5] and low offset voltage suitable for the small amplitude of the physiological signal. On the other hand, CMOS amplifiers provide practically infinite input impedance and ultra-low leakage current. The system also provides three selectable amplifier modes: (a) double-differential amplifier, (b) single-differential amplifier in channel 1, (c) single-differential amplifier in channel 2. The double-differential amplifier provides a high common-mode rejection and adjustable gain for each channel to further reduce common-mode interference. The single-differential amplifier (channel 1 or channel 2) in the recording system are also accessible as differential-input and single-ended output channels. Moreover, the system provides an offset compensation structure to prevent the amplifier from exceeding the input range. The offset compensation system can selectively be turned off to reduce the power consumption.

In recently years, nonvolatile memory with nanocrystals cell have widely applied to overcome the issue of operation and reliability for conventional floating gate memory. The excellent electrical characteristics of memory device need good endurance, long retention time and small operation voltage. Among numerous memory devices with nanocrystals, the memory device with metal nanocrystals was widely researched. It will be new candidate for flash memory. The advantages of metal nanocrystals has have higher density of states around Fermi level, stronger coupling with conduction channel, wide range of available work functions and smaller energy perturbation due to carrier confinement. So metal nanocrystals can reduce operate voltage, and increase write/erase speed and endurance. Most important of all, we can control the sizes of nanocrystals dot and manufacture at low temperature¡CThis advantage can apply to thin film transistor liquid crystal display; it fabricates driving IC and logical IC on panel for diverseness and adds memory beside switch TFT as image storage to reduce power consumption for portability. In this thesis, we will discuss metal nanocrystals as memory storage medium. And we can use high temperature oxidation, low temperature annealing with oxygen to form nanocrystals. Besides we analyze the effect of electron storage at metal nanocrystals by means of material and electrical analysis.

Class D power amplifier applies in high efficiency circuit. In hearing aid system, we require high power efficiency, low-voltage and low-power. The operation of frequency is low frequency. All the circuits are designed based on the TSMC 035 CMOS process technology. The supply voltage is 1.5V and the input signal is 4KHz. Simulation results show that the Class D power efficiency is high efficiency amplifier. When 0.3V of 2KHz input signal is applied, The maximum THD is 0.63% and static current is 4uA and the efficiency is 83.6%.

This thesis includes two topics. The first topic is a low power design of 8-bit ANT-based pipelining CLA. The second one is a small digital to analog converter (DAC) used in an implantable neural stimulator. An ANT-based low-power 8-bit pipelining carry-lookahead adder (CLA) using two-phase all-N-transistor (ANT) blocks which are arranged in a PLA design style with power-aware pipelining is presented. The pull-up charging and pull-down discharging of the transistor arrays of the PLA are accelerated by two feedback MOS transistors between the evaluation NMOS blocks and the outputs. Both the added power-aware clock control circuit and clock generation circuit detecting data transition take advantage of shutting down the processing stages given identical inputs in two consecutive operations by keeping high clock level. The design keeps the advantage of high speed while having the effect of low power dissipation. The implantable neural stimulator assists patients to reconstruct transmission paths of neural signals by current stimulation. The proposed small DAC not only decreases the chip area and power dissipation by reducing transistor count, but also improves the linearity with higher current output performance. All of measured performances of the proposed DAC make the chip worthy of being implemented in a field application.

This thesis includes two research topics. The first topic is a low-power 2-dimensional bypassing digital multiplier design. The second one is a low-power sensorless micro-controller for brushless DC motors (BLDCM). The low-power 2-dimensional bypassing digital multiplier takes advantage of a 2-dimensional bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally partial product or the vertically operand is zero. Hence, it is a 2-dimensional bypassing architecture. Thorough post-layout simulations show that the power dissipation of the proposed 8 ¡Ñ 8 design is reduced by more than 75% compared to the prior 8 ¡Ñ 8 design with obscure cost of delay and area. The goal of the low-power sensorless micro-controller for brushless DC motors is to design a BLDCM controller without using any Hall sensor. Back-EMF estimation method using the terminal voltage sensing is adopted for the detection of the commutation moment for the proper commutation control of the BLDCM. The position of the rotor can be precisely estimated by measuring the back-EMF as well as the zero-crossing points.

When the nerve cell of human is damaged, the central neural system (CNS) can not work properly. Instead of sending commands by CNS, we can use a micro-stimulation method to send commands to hands, legs, or organs. The first part of this thesis presents a fully implantable system for neural micro-stimulation and neural signal monitoring, and introduces the communication protocol and baseband circuitry of the system. Due to the rapidly development of small and portable electrical equipments, low power becomes more and more important because of the limitation of the battery capacity. Meanwhile, the embedded memory in these devices consumes considerable power. In this thesis, we present a low-power sequential memory decoder to resolve the power-dissipation of embedded memories. We¡¦ll verify that the sequential decoder can reduce the power consumption compared to traditional decoders by implementing our idea with a 2-Kbit SRAM memory.