No description available.

No description available.

No description available.

No description available.

No description available.

CMOS technology is particularly attractive for commercialization of ultra wideband (UWB) radios due to its low power and low cost. In addition to CMOS implementation, UWB radios would also significantly benefit from a radio architecture that enables digital communications. In addition to the normal challenges of CMOS RFIC design, there are two major technical challenges for the implementation of CMOS digital UWB radios. The first is building RF and analog circuitry covering wide bandwidth over several GHz. The second is sampling and digitizing high frequency signals in the UWB frequency range of 3 GHz to 10 GHz, which is not feasible for existing CMOS analog-to-digital converters. In this dissertation, we investigate the two technical challenges at the circuit level and the system level. We propose a systematic approach at the circuit level for optimal transistor sizing and biasing conditions that result in optimal noise and power matching over a wide bandwidth. We also propose a general scheme for wideband matching. To verify our methods, we design two single-stage low noise amplifiers (LNAs) in TSMC 0.18µm CMOS technology. Measurement results from fabricated chips indicate that the proposed LNAs could achieve as high as 16 dB power gain and as low as 2.2 dB noise figure with only 6.4 mA current dissipation under a supply voltage of 1.2 V. At the system level, we propose a unique frequency domain receiver architecture. The receiver samples frequency components of a received signal rather than the traditional approach of sampling a received signal at discrete instances in time. The frequency domain sampling leads to a simple RF front-end architecture that directly samples an RF signal without the need to downconvert it into a baseband signal. Further, our approach significantly reduces the sampling rate to the pulse repetition rate. We investigate a simple, low-power implementation of the frequency domain sampler with 1-bit ADCs. Simulation results show that the proposed frequency-domain UWB receiver significantly outperforms a conventional analog correlator. A digital UWB receiver can be implemented efficiently in CMOS with the proposed LNA as an RF front-end, followed by the frequency domain sampler. / Ph. D.

A new coding scheme called "turbo coding" has generated tremendous interest in channel coding of digital communication systems due to its high error correcting capability. Two key innovations in turbo coding are parallel concatenated encoding and iterative decoding. A soft-in soft-out component decoder can be implemented using the maximum a posteriori (MAP) or the maximum likelihood (ML) decoding algorithm. While the MAP algorithm offers better performance than the ML algorithm, the computation is complex and not suitable for hardware implementation. The log-MAP algorithm, which performs necessary computations in the logarithm domain, greatly reduces hardware complexity. With the proliferation of the battery powered devices, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of a turbo decoder based on the log-MAP algorithm. Our turbo decoder has two component log-MAP decoders, which perform the decoding process alternatively. Two major ideas for low-power design are employment of a variable number of iterations during the decoding process and shutdown of inactive component decoders. The number of iterations during decoding is determined dynamically according to the channel condition to save power. When a component decoder is inactive, the clocks and spurious inputs to the decoder are blocked to reduce power dissipation. We followed the standard cell design approach to design the proposed turbo decoder. The decoder was described in VHDL, and then synthesized to measure the performance of the circuit in area, speed and power. Our decoder achieves good performance in terms of bit error rate. The two proposed methods significantly reduce power dissipation and energy consumption. / Master of Science

Structural Health Monitoring (SHM) is the technology of monitoring and assessing the condition of aerospace, civil, and mechanical infrastructures using a sensing system integrated into the structure. Among variety of SHM approaches, impedance-based method is efficient for local damage detection. This thesis focuses on system level concerns for impedance-based SHM. Two essential requirements are reached in the thesis: reduction of power consumption of wireless SHM sensor, and compensation of temperature dependency on impedance. The proposed design minimizes power by employing on-board signal processing, and by eliminating power hungry components such as ADC and DAC. The prototype implemented with MSP430 micro controller is verified to be able to handle SHM operation and wireless communication with extremely low-power: 0.15 mW during the inactive mode and 18 mW during the active mode. Each SHM operation takes about 13 seconds to consume 236 mJ. When our ASN-2 operates once in every four hours, it can run for about 2.5 years with two AAA-size batteries. To compensate for temperature change, we proposed an algorithm to select a small subset of baseline profiles for some critical temperatures and to estimate the baseline profile for a given ambient temperature through interpolation. Experimental results show that our method reduces the number of baseline profiles to be stored by 45%, and estimates the baseline profile of a given temperature accurately. / Master of Science

Power consumption and battery life are of critical importance for medical implant devices. For this reason, devices for Wireless Body Area Network (WBAN) applications must consume very little power. To save power, it is desirable to turn off or put to sleep a device when not in use. However, a transceiver, which is the most power hungry block of a wireless sensor node, needs to listen for the incoming signal continuously. An alternative scheme, is to listen for the incoming signal at a predetermined internal, which saves power at the cost of increased latency. Another and more sophisticated scheme is to provide a wake-up receiver, which listens for the incoming signal continuously, and upon detection of an incoming signal, it wakes the primary transceiver up. A wake-up receiver is typically simple and dissipates little power to make the scheme useful. This thesis proposes a low-power wake-up receiver, which listens for a wake-up signal, identifies the target node, and wakes up the primary receiver only when that specific node is called upon. When a wake up signal is transmitted to all of the nodes on a network, our wake-up receiver allows all the nodes on a network except the targeted node to remain asleep to save power. Several wake-up receiver topologies have been proposed. This work uses a passive Cockcroft-Walton multiplier circuit as an RF envelope detector followed by a simple detector circuit. A novel serial code detector is then used to decode the pulse width modulated input signal to wake-up the designated node. A passive RF front end and simple decoding circuit reduce power consumption substantially at the cost of low sensitivity. The sensitivity of the wake-up receiver can be improved though the addition of an RF amplifier, but at the cost of increased power consumption. / Master of Science

The increasing demand for high data rate devices and many applications in short range high speed communication, attract many RF IC designers to work on 24-GHz transceiver design. The Federal Communication Commission (FCC) also dedicates the unlicensed 24-GHz band for industrial, science, and medical applications to overcome the interference in overcrowded communications and have higher output signal power. LNA is the first building of the receiver and is a very critical building block for the overall receiver performance. The total NF and sensitivity of the receiver mainly depends on the LNAs NF that mandates a very low NF LNA design. Depending on its gain, the noise figure of the next stages can relax. However, the high gain of an LNA enforces the next stages to be more linear since they suffer from larger signal at their input stage and can get saturated easily. Apparently, designing high gain, low noise, and highly linear LNA is very stimulating. In this thesis, a wideband LNA with low noise figure and high linearity has been designed in 8XP 0.13-um SiGe BiCMOS IBM technology. The highlight of this design is proposing the peaking technique, which results in considerable linearity improvement. Loading the LNA with class AB amplifier, power gain experiences a peaking in high input signal swing levels. The next stager after the LNA is the buffer to provide isolation between the LNA and mixer, and also avoid loading of the LNA from the mixer. Instead of using popular emitter follower architecture, another circuit is proposed to have higher gain and linearity. This buffer has two separate out of phase inputs, coming from the LNA and are combined constructively at the output of the buffer. Since the frequency of this design is high, electromagnetic (EM) simulation for pads, interconnects, transmission lines, inductors, and coplanar transmission lines has been completed using Sonnet cad tool to consider all the parasitic and coupling effects. Considering all the EM effects, the LNA has 15 dB gain with 2.9 dB NF and -8.8 dBm input 1-dB compression point. The designed LNA is wideband, covering the frequency range of 12-GHz to 31-GHz. However, the designed LNA, has the capability of having higher gain at the expense of lower linearity and narrower frequency band using different control voltage. As an example peak gain of 29.3 dB at the 3-dB frequency range of 23.8 to 25.8-GHz can be achieved, having 2.3 dB noise figure and -17 dBm linearity. / Master of Science