No description available.

No description available.

No / 5th Generation mobile networks (5G) and mobile communications technologies beyond 2020 will need to be energy aware so as to support services that are likely to be intelligent and bandwidth hungry, as well as to support multi-mode operation (LTE, LTE+, HSDPA, 3G among others) in a HetNet environment. This imposes stringent design requirements on the RF transceiver, a key consumer of power in networks today. This chapter will investigate the key RF subsystems forming part of the 5G RF transceiver, where energy efficiency and full radio flexibility are at the forefront of system design. In particular, we target advanced designs on antenna systems, RF power amplifiers and the challenges facing cross-talk in MIMO architectures.

The FCC allocated the spectrum of 402-405 MHz for MICS (Medical Implant Communication Services) applications in 1999. The regulations for MICS band apply to devices that support the diagnostic and/or therapeutic functions associated with implanted medical electronics. The implanted devices aid organs and control body functions of patients to support specific treatments, and monitor patients continuously so that necessary action can be taken in advance to avoid serious conditions. To enable to use MICS applications, several requirements must be satisfied. An implanted wireless device should have a small size, consume ultra-low power, and achieve the date rate of at least 200 kbps within 2 m distance. The major challenge is to realize ultra-low power devices. Thus the low-power design of the RF circuit is crucial for MICS applications as the power consumption of the wireless devices is mostly contributed by RF circuits. This thesis investigates low-power design of an LNA and a down-conversion mixer of a receiver for MICS applications. The key idea is to stack an LNA and a mixer, while the LNA operates in the normal super-threshold region and the mixer in the sub-threshold region. In addition, a gm-boosting technique with a capacitor cross-coupled at the LNA input stage is also adopted to achieve a low noise figure (NF) and high linearity, which is critical to the overall performance of the receiver. The mixer operating in the sub-threshold region significantly reduces power dissipation and relaxes the voltage headroom without sacrificing the LNA performance. The relaxed voltage headroom enables stack of the LNA and the mixer with a low supply voltage of 1.2 V. The proposed circuit is designed in 0.18 μm RF CMOS technology. The merged LNA and mixer consumes only 1.83 mW, and achieves 21.6 dB power gain. The NF of the block is 3.55 dB at 1 MHz IF, and the IIP3 is -6.08 dBm. / Master of Science

Thesis (MScEng)--Stellenbosch University, 2011. / ENGLISH ABSTRACT: This thesis addresses the complications that are encountered when characterising the performance of differential microwave LNAs. The predominant sources of noise in electronic circuits are introduced and equivalent two-port noise models for active devices are derived. Correlation between noise generators are defined by means of the noise correlation matrix and existing network theory is adapted to include noise analysis of twoport and multi-port networks. Mixed-mode scattering parameters are introduced in order to define the signal performance of differential and common-mode propagation in multi-port networks and, by applying the same theory, the mixed-mode correlation matrix for a three-port dLNA is derived. Furthermore, an expression is derived for de-embedding the differential noise figure of a three-port dLNA using two single ended measurements. Two dLNA designs, both incorporating wideband 180°-Hybrid ring couplers, are discussed and the differential signal and noise performance of the dLNAs are compared to that of their constituent single ended LNAs. / AFRIKAANSE OPSOMMING: Hierdie tesis behandel die komplikasies wat ontwerpers in die gesig staar tydens die karakterisering van mikrogolf differensiële laeruis versterkers. Die hoof ruisbronne in stroombane word bespreek en ekwivalente tweepoortnetwerkmodelle vir aktiewe toestelle word afgelei. Korrelasie tussen ruisbronne word gedefnieer deur middel van ruiskorrelasiematrikse en bestaande tweepoort- en multipoort-netwerkteorie word aangepas om ruismodelle in te sluit. Weens die feit dat differensiële- en gemene-wyse voortplanting van seine voorkom in multipoortnetwerke word gemengde-modus S-parameters behandel. Dieselfde teorie maak dit vervolgens moontlik om die gemengde-modus ruiskorrelasiematriks van ’n drie-poort differensiële laeruis versterker af te lei. Verder word daar ’n wyse voorgestel waarmee die differensiëleruissyfer van ’n drie-poort differensiële laeruis versterker vanuit twee enkel ruissyfermetings bereken kan word. Twee differensiële laeruis versterker ontwerpe, waarvan beide wyeband 180 -differensiaalkoppelaars implementeer, word bespreek en die differensiëlesein- asook die differensiëleruis-werking word vergelyk met die werking van die omsluite ongebalanseerde laeruis versterkers.

<p>Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible.</p><p>A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector.</p><p>The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.</p>

Algunas aplicaciones tales como la radio astronomía y las comunicaciones con el espacio profundo requieren receptores muy sensibles. Esta tesis trata sobre la tecnología criogénica aplicada a la ingeniería de microondas y se centra en el diseño de amplificadores de muy bajo ruido tanto en tecnología híbrida (MIC) como monolítica (MMIC). El trabajo cubre un ancho campo de conocimiento desde la fabricación mecánica y la configuración de los sistemas hasta el diseño y medida de las aplicaciones finales. Comenzando con pautas y consejos para diseñar sistemas criogénicos (criostatos) este documento profundiza en la medida de parámetros-S y ruido. El diseño de circuitos criogénicos se inicia con el estudio de los efectos de las bajas temperaturas sobre los transistores y componentes de microondas centrándose en los dispositivos de fosfuro de indio (InP). El conocimiento adquirido en este estudio se aplica al diseño de amplificadores de muy bajo ruido en banda Ka. / Some applications such as radio astronomy and deep space communications require very sensitive receivers. This dissertation deals with the cryogenic technology applied to the microwave engineering and focuses on the design of very low noise amplifiers both in hybrid (MIC) and monolithic (MMIC) technologies. The work covers a wide field of knowledge from hardware manufacture and system set up to final applications design and measurement. Starting from guidelines and advices to design cryogenic systems (cryostats) this document goes into S-parameters and noise measurements in deep. The design of cryogenic circuits is initialized with the study of the effect of low temperatures on microwave transistors and components focusing in indium-phosphide (InP) devices. The knowledge gained with this study is applied to the design of very low noise amplifiers in Ka-band.

This work extends the technology of amorphous silicon (a-Si) thin film transistors (TFTs) from traditional switching applications to on-pixel signal amplification for large area digital imaging and in particular, is aimed towards enabling emerging low noise, high resolution and high frame rate medical diagnostic imaging modalities such as digital tomosynthesis. A two transistor (2T) pixel amplifier circuit based on a novel charge-gate thin film transistor (TFT) device architecture is introduced to shrink the TFT based pixel readout circuit size and complexity and thus, improve the imaging array resolution and reliability of the TFT fabrication process. The high resolution pixel amplifier results in improved electrical performance such as on-pixel amplification gain, input referred noise and faster readouts. In this research, a charge-gated TFT that operates as both a switched amplifier and driver is used to replace two transistors (the addressing switch and the amplifier transistor) of previously reported three transistor (3T) APS pixel circuits.. In addition to enabling smaller pixels, the proposed 2T pixel amplifier results in better signal-to-noise (SNR) by removing the large flicker noise source associated with the switched TFT and increased pixel transconductance gain since the large ON-state resistance of the switched TFT is removed from the source of the amplifier TFT. Alternate configurations of 2T APS architectures based on source or drain switched TFTs are also investigated, compared, and contrasted to the gate switched architecture using charge-gated TFT. A new driving scheme based on multiple row resetting is introduced which combined with the on-pixel gain of the APS, offers considerable improvements in imaging frame rates beyond those feasible for PPS based pixels. The novel developed 2T APS architectures is implemented in single pixel test structures and in 88 pixel test arrays with a pixel pitch of 100 µm. The devices were fabricated using an in-house developed top-gate TFT fabrication process. Measured characteristics of the test devices confirm the performance expectations of the 2T architecture design. Based on parameters extracted from fabricated TFTs, the input referred noise is calculated, and the instability in pixel transconductance gain over prolonged operation tine is projected for different imaging frame rates. 2T APS test arrays were packaged and integrated with an amorphous selenium (a-Se) direct x-ray detector, and the x-ray response of the a-Se detector integrated with the novel readout circuit was evaluated. The special features of the APS such as non-destructive readout and voltage programmable on-pixel gain control are verified. The research presented in this thesis extends amorphous silicon pixel amplifier technology into the area of high density pixel arrays such as large area medical X-ray imagers for digital mammography tomosynthesis. It underscores novel device and circuit design as an effective method of overcoming the inherent shortcomings of the a-Si material . Although the developed device and circuit ideas were implemented and tested using a-Si TFTs, the scope of the device and circuit designs is not limited to amorphous silicon technology and has the potential to be applied to more mainstream technologies, for example, in CMOS active pixel sensor (APS) based digital cameras.

Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible. A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector. The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.

This work extends the technology of amorphous silicon (a-Si) thin film transistors (TFTs) from traditional switching applications to on-pixel signal amplification for large area digital imaging and in particular, is aimed towards enabling emerging low noise, high resolution and high frame rate medical diagnostic imaging modalities such as digital tomosynthesis. A two transistor (2T) pixel amplifier circuit based on a novel charge-gate thin film transistor (TFT) device architecture is introduced to shrink the TFT based pixel readout circuit size and complexity and thus, improve the imaging array resolution and reliability of the TFT fabrication process. The high resolution pixel amplifier results in improved electrical performance such as on-pixel amplification gain, input referred noise and faster readouts. In this research, a charge-gated TFT that operates as both a switched amplifier and driver is used to replace two transistors (the addressing switch and the amplifier transistor) of previously reported three transistor (3T) APS pixel circuits.. In addition to enabling smaller pixels, the proposed 2T pixel amplifier results in better signal-to-noise (SNR) by removing the large flicker noise source associated with the switched TFT and increased pixel transconductance gain since the large ON-state resistance of the switched TFT is removed from the source of the amplifier TFT. Alternate configurations of 2T APS architectures based on source or drain switched TFTs are also investigated, compared, and contrasted to the gate switched architecture using charge-gated TFT. A new driving scheme based on multiple row resetting is introduced which combined with the on-pixel gain of the APS, offers considerable improvements in imaging frame rates beyond those feasible for PPS based pixels. The novel developed 2T APS architectures is implemented in single pixel test structures and in 88 pixel test arrays with a pixel pitch of 100 µm. The devices were fabricated using an in-house developed top-gate TFT fabrication process. Measured characteristics of the test devices confirm the performance expectations of the 2T architecture design. Based on parameters extracted from fabricated TFTs, the input referred noise is calculated, and the instability in pixel transconductance gain over prolonged operation tine is projected for different imaging frame rates. 2T APS test arrays were packaged and integrated with an amorphous selenium (a-Se) direct x-ray detector, and the x-ray response of the a-Se detector integrated with the novel readout circuit was evaluated. The special features of the APS such as non-destructive readout and voltage programmable on-pixel gain control are verified. The research presented in this thesis extends amorphous silicon pixel amplifier technology into the area of high density pixel arrays such as large area medical X-ray imagers for digital mammography tomosynthesis. It underscores novel device and circuit design as an effective method of overcoming the inherent shortcomings of the a-Si material . Although the developed device and circuit ideas were implemented and tested using a-Si TFTs, the scope of the device and circuit designs is not limited to amorphous silicon technology and has the potential to be applied to more mainstream technologies, for example, in CMOS active pixel sensor (APS) based digital cameras.