Orientador: Luiz Carlos Kretly / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-11T01:55:52Z (GMT). No. of bitstreams: 1 Silva_AndreTavoradeAlbuquerque_D.pdf: 5543671 bytes, checksum: 26990143f84fbd9e80d60304ebc8febc (MD5) Previous issue date: 2008 / Resumo: Este trabalho apresenta dois tópicos de pesquisa, o primeiro é referente ao projeto e desenvolvimento da tecnologia de fabricação de Chaves MEMS (Micro Electro Mechanical System) de RF e o segundo é o projeto de circuitos integrados. No que se refere a chaves MEMS, descreve-se o processo e a metodologia para projeto de Chaves MEMS paralela sobre linha de transmissão coplanar (CPW). A estrutura é composta de uma ponte metálica suspensa em ambos os lados por dois postes metálicos conectados ao plano de terra. As chaves são projetadas para uma baixa tensão de ativação (16 V) e com larga banda de operação em freqüência (400 MHz ¿ 4GHz) possibilitando seu uso na maioria dos padrões de sistemas de comunicação. Também é descrita a metodologia do projeto auxiliado por simulações eletromecânicas e eletromagnéticas e finalmente é apresentada a caracterização de 4 chaves construídas. Após extensa pesquisa na literatura técnico-científica, foi identificado que este é o primeiro trabalho no Brasil dedicado ao desenvolvimento de tecnologia de fabricação de chaves MEMS. Os projetos de circuitos integrados foram realizados em tecnologia CMOS 0,35 µm e incluem: multiplicador de tensão e oscilador em anel, chaveador SPDT (Single Pole Double Through), amplificador de baixo ruído e modulador BPSK. Sendo os circuitos multiplicador de tensão e oscilador em anel projetados para aplicações em chaves MEMS. Os circuitos SPDT, amplificador de baixo ruído e modulador BPSK são parte integrante de Front-End de RF, com recepção em 1,8 GHz (banda D - GSM) e transmissão em 868,3 MHz (padrão Zigbee). São descritos os guias de projeto para cada circuito com simulações e desenho de layout. Especificamente para os circuitos, multiplicador de tensão e amplificador de baixo ruído são apresentadas novas topologias. Estes dois circuitos estão em via de preparação de patente. Finalmente, as caracterizações de cada circuito são apresentadas, com exceção do modulador BPSK / Abstract: This work presents two main research topics: the first refers to the design and the development of a fabrication technology for RF MEMS (Micro Electromechanical Systems) Switches and the second to the design of RF integrated circuits. In relation to MEMS switches, it describes the fabrication process and the design methodology of Shunt MEMS switches over a coplanar transmission line (CPW). The structure is composed by a metallic bridge anchored on both ends by two metallic posts connected to the ground plane. The switches are designed to operate at low activation voltage (16 V) and with a large band of operating frequency (400 MHz ¿ 4GHz), making possible its use in many communication systems. It is also described a design methodology assisted by electromechanical and electromagnetic simulations, and finally it is presented the characterization of 4 switches. After extensive search in technical literature, it was identified that this is the first work in Brazil dedicated to the technology development and fabrication of MEMS switches. The integrated circuits designs are realized in CMOS 0.35 µm technology and includes: charge pump and ring oscillator, SPDT switcher (Single Pole Double Through), low noise amplifier and BPSK modulator. The circuits charge pump and ring oscillator are intended to MEMS switches applications. The circuits SPDT, low noise amplifier and BPSK modulator are integrating parts of a RF Front-End, with reception at 1.8 GHz (band D ¿ GSM) and transmission at 868.3 MHz (ZigBee standard). The design guidelines to each circuit are described, with simulations and layout drawing. Specifically to the circuits charge pump and low noise amplifier, it is presented new topologies with innovation in the area. These two circuits have their patent process under preparation. Finally, the characterization of each circuit is presented, with exception of the BPSK modulator / Doutorado / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

Grace aux récents développements des technologies d’intégration, il est aujourd’hui possible d’envisager la réalisation de circuits et systèmes intégrés sur Silicium fonctionnant à des fréquences auparavant inatteignables. Par conséquence, depuis quelques années, on assiste à la naissance de nouvelles applications en bande millimétrique, comme la communication sans fil à haut-débit à 60GHz, les radars automobiles à 76-77 et 79-82GHz, et l’imagerie millimétrique à 94GHz.Cette thèse vise, en premier lieu, à la définition d’une méthodologie de conception des circuits intégrés en bande millimétrique. Elle est par la suite validée au travers de son application à la conception des amplificateurs faible-bruit en technologie BiCMOS SiGe. Dans ce contexte, une attention particulière a été portée au développement d’une stratégie de conception et de modélisation des inductances localisées. Plusieurs exemples d’amplificateurs faible-bruit ont été réalisés, à un ou deux étages, employant des composants inductifs localisés ou distribués, à 60, 80 et 94 GHz. Tous ces circuits présentent des caractéristiques au niveau de l’état de l’art dans le domaine, ainsi en confirmant l’exactitude de la méthodologie de conception et son efficacité sur toute la planche de fréquence considérée. En outre, la réalisation d’un récepteur intégré pour applications automobiles à 80GHz est aussi décrite comme exemple d’une possible application système, ainsi que la co-intégration d’un amplificateur faible-bruit avec une antenne patch millimétrique intégrée sur Silicium. / The interest towards millimeter waves has rapidly grown up during the last few years, leading to the development of a large number of potential applications in the millimeter wave band, such as WPANs and high data rate wireless communications at 60GHz, short and long range radar at 77-79GHz, and imaging systems at 94GHz.Furthermore, the high frequency performances of silicon active devices (bipolar and CMOS) have dramatically increased featuring both fT and fmax close or even higher than 200GHz. As a consequence, modern silicon technologies can now address the demand of low-cost and high-volume production of systems and circuits operating within the millimeter wave range. Nevertheless, millimeter wave design still requires special techniques and methodologies to overcome a large number of constraints which appear along with the augmentation of the operative frequency.The aim of this thesis is to define a design methodology for integrated circuits operating at millimeter wave and to provide an experimental validation of the methodology, as exhaustive as possible, focusing on the design of low noise amplifiers (LNAs) as a case of study.Several examples of LNAs, operating at 60, 80, and 94 GHz, have been realized. All the tested circuits exhibit performances in the state of art. In particular, a good agreement between measured data and post-layout simulations has been repeatedly observed, demonstrating the exactitude of the proposed design methodology and its reliability over the entire millimeter wave spectrum. A particular attention has been addressed to the implementation of inductors as lumped devices and – in order to evaluate the benefits of the lumped design – two versions of a single-stage 80GHz LNA have been realized using, respectively, distributed transmission lines and lumped inductors. The direct comparison of these circuits has proved that the two design approaches have the same potentialities. As a matter of fact, design based on lumped inductors instead of distributed elements is to be preferred, since it has the valuable advantage of a significant reduction of the circuit dimensions.Finally, the design of an 80GHz front-end and the co-integration of a LNA with an integrated antenna are also considered, opening the way to the implementation a fully integrated receiver.

Les travaux de thèse présentés se situent dans le contexte de la conception de circuits intégrés en technologie CMOS avancée pour des applications radiofréquence à très faible consommation de puissance. Les circuits sont conçus à travers deux concepts. Le premier est l'utilisation du coefficient d'inversion qui permet de normaliser le transistor en fonction de sa taille et de sa technologie, ceci permet une analyse rapide pour différentes performances visées ou différentes technologies. La deuxième approche est d'utiliser un facteur de mérite pour trouver la polarisation la plus adéquate d'un circuit en fonction de ses performances. Ces deux principes ont été utilisés pour définir des méthodes de conception efficaces pour deux blocs radiofréquence : l'amplificateur faible bruit et l'oscillateur. / Thesis work are presented in the context of the integrated circuits design in advanced CMOS technology for ultra low power RF applications. The circuits are designed around two concepts. The first is the use of the inversion coefficient to normalize the transistor as a function of its size and its technology, this allows a quick analysis for different performances or different technologies. The second approach is to use a figure of merit to find the most appropriate polarization of a circuit based on its performance. These two principles were used to define effective design methods for two RF blocks: low noise amplifier and oscillator.

The largest 21st century radio telescope, the Square Kilometre Array (SKA) is now being planned, and the first phase of construction is estimated to commence in the year 2016. Phased array technology, the key feature of the SKA, requires the use of a tremendous number of receivers, estimated at approximately 37 million. Therefore, in the context of this project, the Low Noise Amplifier (LNA) located at the front end of the receiver chain remains the critical block. The demanding specifications in terms of bandwidth, low power consumption, low cost and low noise characteristics make the LNA topologies and their design methodologies one of the most challenging tasks for the realisation of the SKA. The LNA design is a compromise between the topology selection, wideband matching for a low noise figure, low power consumption and linearity. Considering these critical issues, this thesis describes the procedure for designing a monolithic microwave integrated circuit (MMIC) LNA for operation in the mid frequency band (400 MHz to 1.4 GHz) of the SKA. The main focus of this work is to investigate the potential of MMIC LNA designs based on a novel InGaAs/InAlAs/InP pHEMT developed for 1 µm gate length transistors, fabricated at The University of Manchester. An accurate technique for the extraction of empirical linear and nonlinear models for the fabricated active devices has been developed. In addition to the linear and nonlinear model of the transistors, precise models for passive devices have also been obtained and incorporated in the design of the amplifiers. The models show excellent agreement between measured and modelled DC and RF data. These models have been used in designing single, double and differential stage MMIC LNAs. The LNAs were designed for a 50 Ω input and output impedance. The excellent fits between the measured and modelled S-parameters for single and double stage single-ended LNAs reflects the accurate models that have been developed. The single stage LNA achieved a gain ranging from 9 to 13 dB over the band of operation. The gain was increased between 27 dB and 36 dB for the double stage and differential LNA designs. The measured noise figures obtained were higher by ~0.3 to ~0.8 dB when compared to the simulated figures. This is due to several factors which are discussed in this thesis. The single stage design consumes only a third of the power (47 mW) of that required for the double stage design, when driven from a 3 V supply. All designs were unconditionally stable. The chip sizes of the fabricated MMIC LNAs were 1.5 x 1.5 mm2 and 1.6 x 2.5 mm2 for the single and double stage designs respectively. Significantly, a series of differential input to single-ended output LNAs became of interest for use in the Square Kilometre Array (SKA), as it utilises differential output antennas in some of its configurations. The single-ended output is preferable for interfacing to the subsequent stages in the analogue chain. A noise figure of less than 0.9 dB with a power consumption of 180 mW is expected for these designs.

Quelles sont les particules élémentaires et comment l'univers proviennent sont les principales forces motrices de la physique des hautes énergies. Afin de démontrer le modèle standard et découvrez la nouvelle physique, plusieurs détecteurs sont construits pour les expériences en physique des hautes énergies. Capteurs à pixels CMOS offrent un compromis attirant entre la vitesse de lecture, le budget matériel, la tolérance au rayonnement, la consommation d'énergie et la granularité, par rapport aux capteurs à pixels hybrides et des dispositifs à transfert de charge. Ainsi, les CPS sont un bon choix pour détecter les particules chargées dans les détecteurs de vertex et des télescopes de faisceau. La distribution de puissance devient un enjeu important dans les détecteurs à venir, puisque une quantité considérable de capteurs seront installés. Malheureusement, le «Independent Powering» échoue, comme l'approche traditionnelle. Afin de résoudre les problèmes de distribution de puissance et de fournir des tensions silencieuses, cette thèse se concentre sur la conception de la gestion de l'alimentation à faible bruit, à basse consommation d'énergie, de petite taille et sur-puce pleinement pour les CPS. Les CPS sont d'abord introduits en tirer les exigences de conception de la gestion de l'alimentation. La distribution de puissance dédiées à les CPS est ensuite proposé, dans laquelle la gestion de l'alimentation est utilisée comme seconde étape de conversion de puissance. Deux régulateurs sur-puce pleinement sont proposés pour générer la tension d'alimentation analogique et de la tension d'alimentation de référence requis par l'opération d'échantillonnage double corrélé, respectivement. Deux prototypes ont vérifié ces régulateurs. Ils peuvent répondre aux exigences des CPS. En outre, les techniques de gestion de l'alimentation et de la conception tolérance au rayonnement sont également présentés dans cette thèse. / What are the elementary particles and how did the universe originate are the main driving forces in the high energy physics. In order to further demonstrate the standard model and discover new physics, several detectors are built for the high energy physics experiments. CMOS pixel sensors (CPS) can achieve an attractive tradeoff among many performance parameters, such as readout speed, granularity, material budget, power dissipation, radiation tolerance and integrating readout circuitry on the same substrate, compared with the hybrid pixel sensors and charge coupled devices. Thus, the CPS is a good candidate for tracking the charged particles in vertex detectors and beam telescopes.The power distribution becomes an important issue in the future detectors, since a considerable amount of sensors will be installed. Unfortunately, the independent powering has been proved to fail. In order to solve the power distribution challenges and to provide noiseless voltages, this thesis focuses on the design of a low noise, limited area, low power consumption and full on-chip power management in CPS chips. The CPS are firstly introduced drawing the design requirements of the power management. The power distribution dedicated to CPS chips is then proposed, in which the power management is utilized as the second power conversion stage. Two full on-chip regulators are proposed to generate the analog power supply voltage and the reference voltage required by correlated double sampling operation, respectively. Two prototypes have verified these regulators. They can meet the requirements of CPS. Moreover, the power management techniques and the radiation tolerance design are also presented in this thesis.

Ce travail de thèse porte sur la conception, la réalisation et l'étude de sources laser à semi-conducteur de haute cohérence, émettant à 894 nm, pour application aux horloges atomiques Césium compactes pompées optiquement, dans un contexte de développement industriel. Nous nous intéressons plus particulièrement aux lasers à émission par la tranche, dits "Distributed-Feedback" (DFB), pompés électriquement. L'objectif est d'obtenir un laser monomode en fréquence, à faible seuil, à rendement optique élevé et de largeur de raie inférieure à 1 MHz. Nous traitons d'abord de la conception et de la caractérisation au 1er ordre des diodes DFB, jusqu'à leur mise en modules pour horloge, puis nous effectuons une étude approfondie des propriétés physiques de l'émission laser en terme de cohérence temporelle, en introduisant une nouvelle méthode universelle de caractérisation du bruit de fréquence optique. Enfin, nous nous intéressons aux propriétés spectrales de l'émission en configuration d'asservissement sur une raie de fluorescence du Césium ("Dither-Locking"). Nous montrons que les propriétés intrinsèques du composant satisfont aux exigences du système industriel tel qu'il a été défini lors de l'étude. / This PhD work deals with the design, the fabrication and the study of high-coherence semiconductor laser sources emitting at 894 nm, for application to compact, optically-pumped cesium atomic clocks in an industrial context. We are particularly interested in the electrically pumped "Distributed-Feedback" in-plane laser diodes (DFB). The aim is to obtain a low-threshold, single-mode laser with high optical efficiency and a linewidth of less than 1 MHz. We first deal with the design and first-order characterization of the DFB diodes until they are put into modules for the clock. We then carry out an in-depth study of the physical properties of the laser emission in terms of coherence time. For that purpose, a new universal method for characterizing the optical frequency noise is introduced. Finally, we look further into the spectral properties of the emission in a servo configuration on a fluorescence line of the cesium ("Dither-Locking"). We show that the intrinsic properties of the component satisfy the requirements of the industrial system as defined in the study.

This work presents the design of two compact multi-standard low-noise amplifier (LNA) in a 28 nm low-power bulk CMOS process. The transistor parameters were optimized by the Gₘ/ID method taking into account the parasitics and the behavior of highly scaled transistors. To cover the industrial science medical (ISM)-bands around 2.4 and 5.8 GHz, the WLAN band as well as the Kᵤ band a bandwidth enhancement is required. Two versions of LNAs, one with vertical inductors and one with active inductors, are implemented and verified by measurements. The noise figure (NF) exhibits 4.2 dB for the LNA with active inductors and 3.5 dB for the LNA with vertical inductors. The voltage gain reaches 12.8 and 13.4 dB, respectively, with a 3 dB-bandwidth of 20 GHz. Both input referred 1-dB-compression points are higher than 212 dBm making the chips attractive for communication standards with high linearity requirements. The chips consume 53 mW DC power and the LNA with active inductors occupies a core area of only 0.0018 mm², whereas the version with vertical inductors requires 0.021 mm².

No description available.

The master thesis deals with the design of a low noise preamplifier operating in the frequency range from 30 MHz to 1 GHz, usable for measuring and testing of electromagnetic interference in the electromagnetic compatibility test rooms. The introductory, theoretical, part is focused on the analysis and description of the necessary properties of the low noise preamplifier required for the subsequent design. The practical part deals with the selection of suitable components, simulation, design and subsequent realization of low noise preamplifier. At the end of the thesis the design and the final verification measurements are described and discussed.

The aim of this thesis is to introduce innovations and trends in the construction of flexible pavement layers, which are used abroad. The paper is focused on some surfaces, which help to reduce noise pollution from traffic, and binders, which are based on natural ingredients called bioasphalt. It provides an information summary of increasing share of reclaimed asphalt in bituminous mixtures and introduces possible procedures that could lead to an increase in pavement life.