The last two decades have witnessed the CMOS processes and design techniques develop and prosper with unprecedented speed. They have been widely employed in contemporary integrated circuit (IC) commercial products resulting in highly added value. Tremendous e orts have been devoted to extend and optimize the CMOS process and its application for future wireless communication systems. Meanwhile, the last twenty years have also seen the fast booming of the wireless communication technology typically characterized by the mobile communication technology, WLAN technology, WPAN technology, etc. Nowadays, the spectral resource is getting increasingly scarce, particularly over the frequency from 0.7 to 6 GHz, whether the employed frequency band is licensed or not. To combat this dilemma, the ultra wideband (UWB) technology emerges to provide a promising solution for short-range wireless communication while using an unlicensed wide band in an overlay manner. Another trend of obtaining more spectrum is moving upwards to higher frequency bands. The WiFi-Alliance has already developed a certi cation program of the 60-GHz band. On the other side, millimeterwave (mmWave) frequency bands such as 28-GHz, 38-GHz, and 71-GHz are likely to be licensed for next generation wireless communication networks. This new trend poses both a challenge and opportunity for the mmWave integrated circuits design. This thesis combines the state-of-the-art IC and hardware technologies and design techniques to implement and propose UWB and 5G prototyping systems. First of all, by giving a thorough analysis of a transmitted reference pulse cluster (TRPC) scheme and mathematical modeling, a TRPC-UWB transceiver structure is proposed and its features and speci cations are derived. Following that, the detailed design, fabrication and veri cation of the TRPC-UWB transmitter front end and wideband voltage-controlled oscillators (VCOs) in CMOS process is presented. The TRPCUWB transmitter demonstrates a state-of-the-art energy e ciency of 38.4 pJ/pulse. Secondly, a novel system architecture named distributed phased array based MIMO (DPA-MIMO) is proposed as a solution to overcome design challenges for the future 5G cellular user equipment (UE) design. In addition, a prototyping design of on-chip mmWave antenna with radiation e ciency enhancement is presented for the IEEE 802.11ad application. Furthermore, two wideband K-band VCO prototypes based on two di erent topologies are designed and fabricated in a standard CMOS process. They both show good performance at center frequencies of 22.3 and 26.1 GHz. Finally, two CMOS mmWave VCO prototypes working at the potential future 5G frequency bands are presented with measurement results. / Graduate / 2018-04-30 / amenghym@gmail.com

This thesis presents a study of impedance optimisation of active microstrip patch antennas to multiple frequency points. A single layered aperture coupled microstrip patch antenna has been optimised to match the source reflection coefficient of a transistor in designing an active antenna. The active aperture coupled microstrip patch antenna was optimised to satisfy Global Positioning System (GPS) frequency specifications. A rudimentary aperture coupled microstrip patch antenna consists of a rectangular antenna element etched on the top surface of two dielectric substrates. The substrates are separated by a ground plane and a microstrip feed is etched on the bottom surface. A rectangular aperture in the ground plane provides coupling between the feed and the antenna element. This type of antenna, which conveniently isolates any circuit at the feed from the antenna element, is suitable for integrated circuit design and is simple to fabricate. An active antenna design directly couples an antenna to an active device, therefore saving real estate and power. This thesis focuses on designing an aperture coupled patch antenna directly coupled to a low noise amplifier as part of the front end of a GPS receiver. In this work an in-house software package, dubbed ACP by its creator Dr Rod Waterhouse, for calculating aperture coupled microstrip patch antenna performance parameters was linked to HP-EEsof, a microwave computer aided design and simulation package by Hewlett-Packard. An ANSI C module in HP-EEsof was written to bind the two packages. This process affords the client the benefit of powerful analysis tools offered in HP-EEsof and the fast analysis of ACP for seamless system design. Moreover, the optimisation algorithms in HP-EEsof were employed to investigate which algorithms are best suited for optimising patch antennas. The active antenna design presented in this study evades an input matching network, which is accomplished by designing the antenna to represent the desired source termination of a transistor. It has been demonstrated that a dual-band microstrip patch antenna can be successfully designed to match the source reflection coefficient, avoiding the need to insert a matching network. Maximum power transfer in electrical circuits is accomplished by matching the impedance between entities, which is generally acheived with the use of a matching network. Passive matching networks employed in amplifier design generally consist of discrete components up to the low GHz frequency range or distributed elements at greater frequencies. The source termination for a low noise amplifier will greatly influence its noise, gain and linearity which is controlled by designing a suitable input matching network. Ten diverse search methods offered in HP-EEsof were used to optimise an active aperture coupled microstrip patch antenna. This study has shown that the algorithms based on the randomised search techniques and the Genetic algorithm provide the most robust performance. The optimisation results were used to design an active dual-band antenna.

This dissertation presents novel Harmonic Rejection (HR) Mixer architectures to obtain a high level of harmonic rejection. This is achieved by reducing the sensitivity to mismatches in devices operating at high frequencies. Consequently, the HR performance for this mixer architecture is primarily determined by resistor and capacitor matching at low intermediate frequencies (IF). Since large resistor areas can be used at relatively less power penalty in the low frequency IF section, superior HR performance is realized. A design fabricated in 110 nm CMOS process, rejects up to the fi rst 14 local oscillator (LO) harmonics and achieves 3rd, 5th and 7th HR ratios in excess of 52, 54 and 55 dB respectively, without any calibration or trimming. This mixer architecture also rejects flicker noise, has improved image rejection (IR) and second-order input-intercept-point (IIP2) performance. By using a clock N times the desired LO frequency, this scheme rejects the (N-1)th LO harmonic only by an amount of 20log(N-1) dB. A new technique is presented that enables better HR for the (N-1)th harmonic while preserving the level of rejection for other harmonics. This mixer fabricated in 55 nm standard CMOS process has a programmable number of 8, 10, 12 or 14 mixer phases and achieves an improvement of 29 dB for the (N-1)th harmonic while achieving 52 dB of rejection for the 3rd harmonic. It also rejects flicker noise and has an IIP2 performance of 68 dBm. The mixers presented in this dissertation set the state-of-the-art in HR performance for single-stage mixers with configurable number of phases without using any calibration or trimming. / text

Στη διατριβή αυτή προτείνονται, αναλύονται και υλοποιούνται εναλλακτικές τοπολογίες για δυο από τα κύρια υποσυστήματα ενός πομποδέκτη, τον τοπικό ταλαντωτή και τον ενισχυτή χαμηλού θορύβου. Το κύριο σύστημα που εξετάζεται είναι αυτό του τοπικού ταλαντωτή, όπου μελετούνται και υλοποιούνται τοπολογίες ταλαντωτών και βρόχων που λειτουργούν υπό εμβολή, με κύριο προσανατολισμό την ελαχιστοποίηση του θορύβου φάσης. Ο προτεινόμενος βρόχος εμβολής προσφέρει την δυνατότητα χρησιμοποίησής του σε multiband συστήματα με ταυτόχρονη μάλιστα λειτουργία στις ζώνες των 2.4 GHz και 5.2 GHz για την περίπτωση των ασύρματων τοπικών δικτύων. Ένας τέτοιος βρόχος μπορεί να συμβάλει καθοριστικά στην ελαχιστοποίηση του μεγέθους και της κατανάλωσης του συνολικού multiband συστήματος. Προτείνεται και υλοποιείται ένας ταλαντωτής εμβολής (injection-locked oscillator) και διερευνάται η δυνατότητά του να λειτουργεί παράλληλα και ως μίκτης δίνοντας ένα κύκλωμα πολλαπλών λειτουργιών και εφαρμογών. Το κύκλωμα αυτό ανάλογα με τα σήματα που εμφανίζονται στην είσοδό του λειτουργεί ως απλός ταλαντωτής, ως ταλαντωτής εμβολής, ή ως ίδιο-ταλαντούμενος μίκτης. Προτείνεται και υλοποιείται βρόχος εμβολής (injection-locked phase-locked loop, ILPLL) και μελετάται η βελτίωση στον θόρυβο φάσης και την περιοχή κλειδώματος. Στα πλαίσια των ILPLL μελετώνται και υλοποιούνται βρόχοι εμβολής στην θεμελιώδη συχνότητα και βρόχοι υπό-αρμονικής (sub-harmonic) εμβολής (s-ILPLL). Ο βρόχος υπό-αρμονικής εμβολής χρησιμοποιεί σήμα εμβολής στα 2.5 GHz και παράγει συχνότητα εξόδου 5 GHz. Στα πλαίσια της διερεύνησης του θορύβου φάσης σε συστήματα τοπικών ταλαντωτών μελετάται η διάταξη του συνθέτη διπλού βρόχου και αναπτύσσεται μία πρωτότυπη τοπολογία με καλύτερα χαρακτηριστικά στον θόρυβο φάσης σε σύγκριση με τις κλασικές αρχιτεκτονικές διπλού βρόχου. Σε όλες τις παραπάνω διατάξεις, παρουσιάζονται, η μαθηματική ανάλυση για τον θόρυβο φάσης και τα αποτελέσματα των θεωρητικών υπολογισμών. Η ορθότητα των προτάσεων και η λειτουργία των προτεινόμενων διατάξεων επαληθεύεται με μετρήσεις των πειραματικών πρωτοτύπων. Τέλος, στα πλαίσια της διατριβής προτείνεται ένας ενισχυτής χαμηλού θορύβου που περιλαμβάνει κύκλωμα ελέγχου του κέρδους, το οποίο δίνει την δυνατότητα στο σύστημα να «επιλέξει» την επιθυμητή ενίσχυση ανάλογα με τις συνθήκες, μειώνοντας έτσι σημαντικά την κατανάλωση σε περιπτώσεις όπου αυτό είναι δυνατό. Περιλαμβάνει επίσης και φίλτρο απόρριψης ειδώλου που ελέγχεται από εξωτερική τάση συντονισμού. / In this dissertation we propose, study and develop alternative topologies for two of the most important blocks of a Front-End, the Local Oscillator and the Low Noise Amplifier. We are mainly concerned with the analysis of various local oscillator topologies, studying the phase noise and the injection-locking performance of oscillators and phase-locked loops. The overall performance of the experimental design demonstrates the applicability of the proposed approach to the development of dual-band synthesizers (2.4 GHz and 5.2 GHz), which constitute very important subsystems for modern multiband/multistandard transceivers in WLAN applications. We propose and develop an injection locked oscillator (ILO) and investigate the ability to operate simultaneously as a mixer resulting in a multifunctional circuit. The proposed circuit topology operates as: a) a free-running oscillator, b) both an injection-locked oscillator and a subharmonic injection-locked oscillator (s-ILO), c) both a self-oscillating mixer and a harmonic self-oscillating mixer (h-SOM), and d) a subharmonic injection-locked self-oscillating mixer (s-ILSOM). We propose and develop a different approach for ILPLL design at 5 GHz by applying a technique used in optical communications. We newly address the phase-noise analysis using the loop linear model and compare the results with previously reported work. Furthermore, we address the phase noise improvement of subharmonic ILPLLs, especially for the 5-GHz band. Theoretical analysis and computer calculations demonstrate an improved performance for phase noise and power consumption. We present the analysis and experimental evaluation of a modified dual-loop phase locked loop synthesizer, using the phase noise transfer functions resulting from the linear model of the synthesizer. The different arrangement in the high frequency loop, in contrast to previous reported series-connected dual-loop topologies, offers various advantages, such as improved phase noise, finer resolution and lower spurious levels. Discrete elements are used to implement a prototype system for testing. This adds to the flexibility of the design and allows for experimental optimisation of the loop trade-offs. The synthesizer generates signals in the 4850 MHz to 5050 MHz range with a 10 MHz resolution and can match the specifications for wireless LANs operating at 5 GHz. The design resulted in a prototype with very good characteristics suitable for future integration. For all the proposed topologies we present the mathematical analysis and calculated results for the phase noise. Measurement results illustrate the validity of the proposed analyses, demonstrate the main characteristics, and confirm the feasibility of the proposed systems. Finally, a bipolar Low Noise Amplifier (LNA) is designed in this thesis. The IC contains the LNA core, an externally programmed bias network and an image rejection filter. The externally programmed bias network allows the user to select the bias current in an adaptive manner, depending upon the requirements of the individual system. (Low NF, high gain, low consumption etc). Furthermore, the chip can be powered down by sending an appropriate bit stream to the bias network.

What are the elementary particles and how did the universe originate are the main driving forces in the high energy physics. In order to further demonstrate the standard model and discover new physics, several detectors are built for the high energy physics experiments. CMOS pixel sensors (CPS) can achieve an attractive tradeoff among many performance parameters, such as readout speed, granularity, material budget, power dissipation, radiation tolerance and integrating readout circuitry on the same substrate, compared with the hybrid pixel sensors and charge coupled devices. Thus, the CPS is a good candidate for tracking the charged particles in vertex detectors and beam telescopes.The power distribution becomes an important issue in the future detectors, since a considerable amount of sensors will be installed. Unfortunately, the independent powering has been proved to fail. In order to solve the power distribution challenges and to provide noiseless voltages, this thesis focuses on the design of a low noise, limited area, low power consumption and full on-chip power management in CPS chips. The CPS are firstly introduced drawing the design requirements of the power management. The power distribution dedicated to CPS chips is then proposed, in which the power management is utilized as the second power conversion stage. Two full on-chip regulators are proposed to generate the analog power supply voltage and the reference voltage required by correlated double sampling operation, respectively. Two prototypes have verified these regulators. They can meet the requirements of CPS. Moreover, the power management techniques and the radiation tolerance design are also presented in this thesis.

About 50 million people worldwide suffer from epilepsy and one third of them have seizures that are refractory to medication. In the past few decades, deep brain stimulation (DBS) has been explored by researchers and physicians as a promising way to control and treat epileptic seizures. To make the DBS therapy more efficient and effective, the feedback loop for titrating therapy is required. It means the implantable DBS devices should be smart enough to sense the brain signals and then adjust the stimulation parameters adaptively. This research proposes a signal-sensing channel configurable to various neural applications, which is a vital part for a future closed-loop epileptic seizure stimulation system. This doctoral study has two main contributions, 1) a micropower low-noise neural front-end circuit, and 2) a low-power configurable neural recording system for both neural action-potential (AP) and fast-ripple (FR) signals. The neural front end consists of a preamplifier followed by a bandpass filter (BPF). This design focuses on improving the noise-power efficiency of the preamplifier and the power/pole merit of the BPF at ultra-low power consumption. In measurement, the preamplifier exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of bandwidth (BW), 5.86-μVrms input-referred noise in AP mode, while showing 39.4-dB DC gain, 0.36 Hz to 1.3 kHz of BW, 3.07-μVrms noise in FR mode. The preamplifier achieves noise efficiency factor (NEF) of 2.93 and 3.09 for AP and FR modes, respectively. The preamplifier power consumption is 2.4 μW from 2.8 V for both modes. The 6th-order follow-the-leader feedback elliptic BPF passes FR signals and provides -110 dB/decade attenuation to out-of-band interferers. It consumes 2.1 μW from 2.8 V (or 0.35 μW/pole) and is one of the most power-efficient high-order active filters reported to date. The complete front-end circuit achieves a mid-band gain of 38.5 dB, a BW from 250 to 486 Hz, and a total input-referred noise of 2.48 μVrms while consuming 4.5 μW from the 2.8 V power supply. The front-end NEF achieved is 7.6. The power efficiency of the complete front-end is 0.75 μW/pole. The chip is implemented in a standard 0.6-μm CMOS process with a die area of 0.45 mm^2. The neural recording system incorporates the front-end circuit and a sigma-delta analog-to-digital converter (ADC). The ADC has scalable BW and power consumption for digitizing both AP and FR signals captured by the front end. Various design techniques are applied to the improvement of power and area efficiency for the ADC. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588-μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6-μm CMOS process. The die size is 11.25 mm^2. The proposed circuits can be extended to a multi-channel system, with the ADC shared by all channels, as the sensing part of a future closed-loop DBS system for the treatment of intractable epilepsy.

La Magneto-Impédance Géante (GMI) consiste en une forte variation de l’impédance d’un matériau ferromagnétique doux parcouru par un courant d’excitation alternatif haute fréquence lorsqu’il est soumis à un champ magnétique extérieur. Ce travail de thèse introduit de nouvelles techniques numériques et les pistes d’optimisation associées pour les capteurs GMI à haute sensibilité. L'originalité réside dans l'intégration d'un synthétiseur de fréquence et d'un récepteur entièrement numérique pilotés par un processeur de traitement de signal. Ce choix instrumental se justifie par le souhait de réduire le bruit de l’électronique de conditionnement qui limite le niveau de bruit équivalent en champ. Ce dernier caractérise le plus petit champ mesurable par le capteur. Le système de conditionnement conçu est associé à la configuration magnétique off-diagonal pour accroître la sensibilité intrinsèque de l’élément sensible. Cette configuration magnétique consiste en l’utilisation d’une bobine de détection autour du matériau ferromagnétique. Cette association permet en outre d’obtenir une caractéristique impaire de la réponse du capteur autour du champ nul, et par conséquent de pouvoir mettre en œuvre et d’utiliser le capteur sans avoir recours à une polarisation magnétique. Ce choix permet ainsi d’éliminer, ou au moins de minimiser les problématiques liées aux offsets des dispositifs GMI, tout en validant l’intérêt de cette configuration magnétique, notamment sur le choix du point de fonctionnement. Une modélisation des performances en bruit de toute la chaîne de mesure, incluant le système de conditionnement numérique, est réalisée. Une comparaison entre les niveaux de bruit équivalent en champ attendus par le modèle et mesurés est effectuée. Les résultats obtenus ont permis de dégager des lois générales d’optimisation des performances pour un capteur GMI numérique. Partant de ces pistes d’optimisation, un prototype de capteur complet et optimisé a été implémenté sur FPGA. Ce capteur affiche un niveau de bruit équivalent en champ de l’ordre de 1 pT/√Hz en zone de bruit blanc. En outre, ce travail permet de valider l’intérêt des techniques numériques dans la réalisation de dispositifs de mesure à haute sensibilité. / The Giant Magneto-Impedance (GMI) is a large change of the impedance of some soft ferromagnetic materials, supplied by an alternating high-frequency excitation current, when they are submitted to an external magnetic field. This thesis presents the design and performance of an original digital architecture for high-sensitivity GMI sensors. The core of the design is a Digital Signal Processor (DSP) which controls two other key elements: a Direct Digital Synthesizer (DDS) and a Software Defined Radio (SDR) or digital receiver. The choice of these digital concepts is justified by the will to reduce the conditioning electronics noise that limits the equivalent magnetic noise level. The latter characterizes the smallest measurable field by the sensor. The developed conditioning system is associated with the off-diagonal magnetic configuration in order to increase the intrinsic sensitivity of the sensitive element. This magnetic configuration consists of the use of an additional a pick-up coil wound around the ferromagnetic material. This association also makes it possible to obtain an asymmetrical characteristic (odd function) of the sensor response near the zero-field point and to consequently allow for sensor implementation and use without any bias magnetic field. Thus, this choice eliminates, or at least minimizes, the problems related to the offset cancelling of the GMI devices. Also, it validates the advantage of this magnetic configuration, especially the choice of the operating point. Modeling of the noise performance of the entire measurement chain, including the digital conditioning, is performed. A comparison between the expected and measured equivalent magnetic noise levels is then carried out. The results yield general optimization laws for a digital GMI sensor. Using these laws, an optimized prototype of a GMI sensor is designed and implemented on FPGA. An equivalent magnetic noise level in a white noise zone region of approximately 1 pT/√ Hz is obtained. Furthermore, this work also makes it possible to validate the interest of digital techniques in the realization of a high-sensitivity measuring devices.

Le travail de thèse a consisté, en priorité, à s’approprier les technologies d’intégration verticale en usage dans l’industrie pour réaliser des mémoires à plusieurs étages, et à en évaluer l’apport pour les capteurs à pixel CMOS (CPS). Cette approche s’appuie sur la capacité de l’industrie à interconnecter des puces amincies empilées les unes sur les autres. Elle ouvre la perspective d’associer plusieurs microcircuits superposés à un même pixel, en dépits de sa taille réduite. L’interconnexion est donc réalisée au niveau du pixel. Ce saut technologique permet de lever la majorité des obstacles à l’obtention de performances optimales des CPS. On peut en particulier combiner des puces réalisées dans des technologies CMOS très différentes, chacune optimale pour une fonctionnalité précise. La collection des charges du signal peut ainsi être réalisée dans une couche dédiée, les microcircuits de conditionnement analogique des signaux peuvent être concentrés dans une autre couche, une troisième couche pouvant héberger les parties numériques assurant la compression puis la transmission des signaux, etc. Ce progrès se traduit notamment par la possibilité de combiner haute résolution spatiale et lecture rapide, avec une amélioration probable de la tolérance aux rayonnements intenses.On s’affranchit de cette manière des limitations provenant des paramètres de fabrication des fondeurs, qui ne permettent pas à l’heure actuelle, de pleinement exploiter le potentiel des CPS à l’aide d’une technologie CMOS unique. / The thesis has been a priority as taking ownership of vertical integration technologies used in the industry to realize a multistage development, and to evaluate the contributions on CMOS pixel sensors (CPS). 3D integration technologies (3DIT) provide a way to mitigate this hampering correlation between speed and resolution, since they allow to staple layers of readout circuitry on top of the sensing layer, which results in a drastic increase of the functionalities located in (the shadow of) each pixel. A multi-layer structure allows for a higher spatial resolution because more and more transistors may be integrated vertically in a relatively small pixel. Moreover, bringing the components of the sensor closer to each other translates in a faster readout, owing to the reduction in the average length of the inner connecting wires. Vertical integration also opens up the possibility of combining different technologies best suited to each of the sensor main functionalities (signal sensing, analog and digital signal processing and transmission). It overcomes the limitations in this way from the foundry manufacturing parameters, which do not allow to fully exploit the potential ofCPS with a single CMOS technology. 3D-CPS are thus expected to overcome most of the limitations of standard 2DCPS, and are therefore suspected to over new perspectives for the innermost layer of the ILC vertex detector.

L’objectif de ce travail est de concevoir et de caractériser un front-end millimétriqueutilisant des lignes de propagation à ondes lentes S-CPW optimisées en technologies CMOS avancées.Ces lignes présentant des facteurs de qualité 2 à 3 fois supérieurs à ceux des lignes classiques de typemicroruban ou CPW.Dans le premier chapitre, l’impact de l’évolution des noeuds technologiques CMOS sur lesperformances des transistors MOS aux fréquences millimétriques et sur les lignes de propagation ainsiqu’un état de l’art concernant les performances des front-end sont présentés. Le deuxième chapitreconcerne la réalisation des lignes S-CPW dans différentes technologies CMOS et la validation d’unmodèle phénoménologique électrique équivalent. Le troisième chapitre est dédié à la conceptiond’amplificateurs de puissance à 60 GHz utilisant ces lignes S-CPW en technologies CMOS 45 et65 nm. Cette étude a permis de mettre en évidence l’apport des lignes à ondes lentes aux performancesdes amplificateurs de puissance fonctionnant dans la gamme des fréquences millimétriques. Uneméthode de conception basée sur les règles d’électro-migration et permettant une optimisation desperformances a été développée. Finalement, un amplificateur faible bruit et un commutateur d’antennetravaillant à 60 GHz et à base de lignes S-CPW ont été conçus en technologie CMOS 65 nm afin degénéraliser l’impact de ce type de lignes sur les performances des front-end millimétriques. / The objective of this work is to design and characterize a millimeter-wave front-end usingthe optimized slow-wave transmission lines S-CPW in advanced CMOS technologies. The qualityfactor of these transmission lines is twice to three times higher than that of the conventionaltransmission lines such as microstrip lines and coplanar waveguides.In the first chapter, the influence of CMOS scaling-down on the performance of transistors atmillimeter-wave frequencies and on the transmission lines was studied. In addition, a state of the artwith regard to the performance of the front-end was presented. The second chapter concerns about therealization of the S-CPW lines in different CMOS technologies and the validation of an electricalequivalent model. The third chapter is dedicated to the design of 60-GHz power amplifiers using theseS-CPW lines in CMOS 45 and 65 nm technologies. This study highlighted the performanceenhancement of power amplifiers operating at millimeter-wave frequencies by using the slow-wavetransmission lines. A design method based on the electro-migration rules was also developed. Finally,a low noise amplifier and an antenna switch operating at 60 GHz were designed in CMOS 65 nm inorder to generalize the impact of such transmission lines on the performance of the millimeter-wavefront-end.

Ce travail de thèse a pour objectif principal d'améliorer la sensibilité d'un micro-récepteur RMN implantable, utilisé dans le cadre de la micro-spectroscopie localisée in vivo. Dans la première partie de cette thèse, nous avons réexaminé la fabrication et modélisation de ce micro-récepteur par rapport à sa sensibilité. Parmi les deux procédés de fabrication proposés (électrodéposition du micro-récepteur avec un underpass sur un substrat de silicium et de verre), nous avons retenu celui-qui nous a permis d'obtenir les meilleures performances en termes de facteur de qualité. Les prototypes fabriqués avec ce procédé ont été caractérisés à l'aide d'un modèle que nous avons développé, basé sur une équation à coefficients polynomiaux. Ceux-ci ont été établis à partir de la simulation du layout du capteur et ont été réajustés en fonction des mesures. Ce modèle polynomial nous a conduits à un circuit équivalent du micro-récepteur, permettant d'approfondir l'étude de son comportement électrique en radio fréquences. La deuxième partie de ce travail est développée autour de l'association d'un amplificateur faible bruit (LNA) au plus près du micro-récepteur, afin d'améliorer sa sensibilité. Nous avons analysé l'état de l'art de l'amplification de micro-bobines RMN ainsi que l'interaction électromagnétique entre un circuit intégré et l'environnement RMN. En partant de cette analyse et des contraintes à remplir par le circuit d'adaptation (en termes de transmission de puissance, gain en tension et adaptation faible bruit), nous avons proposé un circuit d'amplification locale permettant d'améliorer la sensibilité du capteur. Nous avons validée notre démarche par simulation (avec notre micro-récepteur) et nous avons vérifié l'intérêt de celle-ci en RMN (avec une bobine de surface). Les résultats de ce travail nous ont permis d'établir des solutions concrètes pour atteindre la sensibilité nécessaire à nos applications / The aim of this thesis is to improve the sensitivity of an implantable micro NMR sensor, dedicated to the in vivo local micro-spectroscopy. In the first part of this thesis, we re-examined the design and modeling of this micro-sensor according to its sensitivity. We proposed two micromachining processes (electrodeposition of the micro-sensor with an underpass on a silicon and glass substrate) and we kept the one allowing the higher quality factor. The prototypes made with the chosen process were characterized thanks to a model that we developed, based in an equation with polynomial coefficients. These coefficients were determined from the layout of the sensor and were adapted to match the measurements. From this polynomial model, we proposed an equivalent circuit of the micro-sensor to have a better knowledge of its electrical behavior at high frequencies. The second part of this work is about the closer association of a low noise amplifier (LNA) with the micro-sensor to improve its sensitivity. We analyzed the state of art on the amplification of NMR micro-coils and the electromagnetic interaction between the integrated circuits ant the NMR environment. From this analysis and the conditions of the matching network (power transmission, voltage gain and low noise matching), we proposed a local amplification circuit achieving the sensitivity improvement of the sensor. This approach was validated by simulation (with our micro-sensor) and verified in an NMR system (with a surface coil). The results of this work allow us to set practical solutions to reach the required sensitivity of our applications