The diploma thesis is focused on an experimental design of low-noise asphalt mixtures. The theoretical part describes the problems of noise and methods for noise measurements. There are also specified the characteristics of various low-noise asphalt mixtures. The practical part addresses the experimental design of SMA 8 LA. Subsequently, the mixture is exposed to functional testing and the results are afterwards compared with the conventional type of stone mastix asphalt SMA 8 S. The second part is focused primarily on an experimental mixture design of a specific asphalt mixture type - coated macadam. There is especially solved the issue ofbinder drainage and the proportion of cracked grains during the compaction. The advantage of this mixture is the lower price demands cause by lower binder content and a smaller amount of fine aggregate. This mixture should be used as a base layer for low-loaded (traffic) roads. In the conclusion are thereafter evaluated the knowledge and the experience with the testing and designing of individual mixtures gained during the testing.

<p>Nisko-šumni pojačavač (NŠP) nalazi se u prijemnom delu bežičnog<br />primopredajnika neposredno nakon antene. NJegova uloga je da ulazni<br />signal određene frekvencije i male snage izdvoji i pojača iznad nivoa<br />šuma prijemnika. U okviru doktorske disertacije prikazane su i<br />opisane metode za projektovanje širokopojasnih (UWB) NŠP u CMOS<br />tehnologiji. Ukupno je predloženo devet novih konfiguracija NŠP. Na<br />osnovu dobijenih rezultata, u 0,18 &mu;m UMC CMOS tehnologiji<br />realizovan je i fabrikovan NŠP jednostavne topologije, koja<br />predstavlja zbir dva pristupa, pojačavačkog stepena kaskodne<br />strukture sa povratnom spregom i stepena sa višestrukim<br />iskorišćenjem struje. NŠP je projektovan za frekvencijski opseg od<br />3,1 do 5 GHz. Takođe, opisana je metoda za merenje parametara NŠP, a<br />zatim je i izvršena njegova karakterizacija.</p> / <p>In the transceiver chain the low noise amplifier (LNA) is placed in the frontend<br />of the receiver after the antenna. The LNA needs to isolate and amplify<br />received weak signal at a specific frequency above the noise level of the<br />receiver. In the scope of this doctoral dissertation methods for designing<br />ultra-wideband (UWB) LNA in CMOS technology are presented and<br />described. Nine new LNA configurations were proposed. Based on the<br />obtained results, simple LNA configuration, obtained by merging casode<br />feedback topology and current-reuse technique, was realized and fabricated<br />in 0.18 &mu;m UMC CMOS technology. The LNA is designed for the frequency<br />band from 3.1 to 5 GHz. In addition, the method for measurement LNA<br />parameters is described and the proposed LNA was characterized.</p>

Although the majority of wireless receiver subsystems have moved to digital signal processing over the last decade, the low noise amplifier (LNA) remains a crucial analogue subsystem in any design being the dominant subsystem in determining the noise figure (NF) and dynamic range of the receiver as a whole. In this research a novel LNA configuration, namely the LC-ladder and capacitive shunt-shunt feedback topology, was proposed for use in the implementation of very wideband LNAs. This was done after a thorough theoretical investigation of LNA configurations available in the body of knowledge from which it became apparent that for the most part narrowband LNA configurations are applied to wideband applications with suboptimal results, and also that the wideband configurations that exist have certain shortcomings. A mathematical model was derived to describe the new configuration and consists of equations for the input impedance, input return loss, gain and NF, as well as an approximation of the worst case IIP3. Compact design equations were also derived from this model and a design strategy was given which allows for electronic design automation of a LNA using this configuration. A process for simultaneously optimizing the circuit for minimum NF and maximum gain was deduced from this model and different means of improving the linearity of the LNA were given. This proposed design process was used successfully throughout this research. The accuracy of the mathematical model has been verified using simulations. Two versions of the LNA were also fabricated and the measured results compared well with these simulations. The good correlation found between the calculated, simulated and measured results prove the accuracy of the model, and some comments on how the accuracy of the model could be improved even further are provided as well. The simulated results of a LNA designed for the 1 GHz to 18 GHz band in the IBM 8HP process show a gain of 21.4 dB and a minimum NF of only 1.7 dB, increasing to 3.3 dB at the upper corner frequency while maintaining an input return loss below -10 dB. After steps were taken to improve the linearity, the IIP3 of the LNA is -14.5 dBm with only a small degradation in NF now 2.15 dB at the minimum. The power consumption of the respective LNAs are 12.75 mW and 23.25 mW and each LNA occupies a chip area of only 0.43 mm2. Measured results of the LNA fabricated in the IBM 7WL process had a gain of 10 dB compared to an expected simulated gain of 20 dB, however significant path loss was introduced by the IC package and PCB parasitics. The S11 tracked the simulated response very well and remained below -10 dB over the feasible frequency range. Reliable noise figure measurements could not be obtained. The measured P1dB compression point is -22 dBm. A 60 GHz LNA was also designed using this topology in a SiGe process with ƒT of 200 GHz. A simulated NF of 5.2 dB was achieved for a gain of 14.2 dB and an input return loss below -15 dB using three amplifier stages. The IIP3 of the LNA is -8.4 dBm and the power consumption 25.5 mW. Although these are acceptable results in the mm-wave range it was however found that the wideband nature of this configuration is redundant in the unlicensed 60 GHz band and results are often inconsistent with the design theory due to second order effects. The wideband results however prove that the LC-ladder and capacitive shunt-shunt feedback topology is a viable means for especially implementing LNAs that require a very wide operating frequency range and also very low NF over that range. / Thesis (PhD(Eng))--University of Pretoria, 2011. / Electrical, Electronic and Computer Engineering / unrestricted

This thesis demonstrates that the composite cascode differential stage, operating in the subthreshold region, can form the basis of a high gain (113 dB) and low-power op amp (28.1 µW). The circuit can be fabricated without adding a compensation capacitance. The advantages of this architecture include high voltage gain, low bandwidth, low harmonic distortion, low quiescent current and power, and small chip area. These advantages suggest that this design might be well-suited for biomedical applications where low power, low noise bio-signal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range is required.

The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (VT) shift and 25% to electron mobility (μn) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and iii device aging such as threshold voltage shift and electron mobility degradation. Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.

The survival rate for a suddent cardiac arrest (SCA) is incredibly low, with less than one in ten surviving; most SCAs occur outside of a hospital setting. There is a need to develop an effective and efficient system that can sense, communicate and remediate potential SCA situations on a near real-time basis. This research presents a novel Zeolite-PDMS-based optically unobtrusive flexible dry electrodes for biosignal acquisition from various subjects while at rest and in motion. Two zeolite crystals (4A and 13X) are used to fabricate the electrodes. Three different sizes and two different filler concentrations are compared to identify the better performing electrode suited for electrocardiogram (ECG) data acquisition. A low-power, low-noise amplifier with chopper modulation is designed and implemented using the standard 180nm CMOS process. A commercial off-the-shelf (COTS) based wireless system is designed for transmitting ECG signals. Further, this dissertation provides a framework for Machine Learning Classification algorithms on large, open-source Arrhythmia and SCA datasets. Supervised models with features as the input data and deep learning models with raw ECG as input are compared using different methods. The machine learning tool classifies the datasets within a few minutes, saving time and effort for the physicians. The experimental results show promising progress towards advancing the development of a wireless ECG recording system combined with efficient machine learning models that can positively impact SCA outcomes.

No description available.

The integration of wireless communication, e.g., in real- or quasi-real-time applications, is related to many challenges such as energy consumption, communication range, quality of service, and reliability. The improvement of wireless sensor networks (WSN) performance starts by enhancing the capabilities of each sensor node. To minimize latencies without increasing energy consumption, wake-up receiver (WuRx) nodes have been introduced in recent works since they can be always-on or power-gated with short latencies by a power consumption in the range of some microwatts. Compared to standard receiver technologies, they are usually characterized by drawbacks in terms of sensitivity. To overcome the limitation of the sensitivity ofWuRxs, a design of a low noise amplifier (LNA) with several design specifications is required. The challenging task of the LNA design is to provide equitable trade-off performances such as gain, power consumption, the noise figure, stability, linearity, and impedance matching. The design of fast settling LNA for a duty-cycled WuRx front-end operating at a 868 MHz frequency band is investigated in this work. The paper details the trade-offs between design challenges and illustrates practical considerations for the simulation and implementation of a radio frequency (RF) circuit. The implemented LNA competes with many commercialized designs where it reaches single-stage 12 dB gain at a 1.8 V voltage supply and consumes only a 1.6 mA current. The obtained results could be made tunable by working with off-the-shelf components for different wake-up based application exigencies.

The Master’s thesis is focused on low-noise asphalt mixtures in general, namely asphalt concrete for very thin layers with low noise (BBTM 8 NH) and stone mastic asphalt with low noise (SMA 8 NH). The first half of the thesis describes basic types of asphalt mixtures with low noise, requirements for raw materials (aggregates and asphalt), noise emissions and their measurement methods. The second part deals the design of BBTM 8 NH and SMA 8 NH so that they have the same voids. Subsequently, their parameters were tested. Acoustic absorption, resistence against permanent deformation and stiffness. Test methods are described and evaluated.

Silicon-on-Insulator (SOI) CMOS technology constitutes a good candidate for mixed signal RF CMOS applications. Due to its low junction capacitance and reduced leakage current, SOI provides reduced static and dynamic power consumption of the digital logic combined with increased cut-off frequencies. Moreover, in terms of passive device integration the major benefit of SOI when compared to the conventional bulk is the possibility to use a high resistivity substrate which allows a drastic reduction of substrate losses allowing a high quality factor of the passive devices. Another issue is the harsh environment applications. Electronics capable of operating at high temperatures are required in several industrial applications, including the automobile industry, the aerospace industry, the electrical and nuclear power industries, and the well-logging industry. The capability of SOI circuits to expand the operating temperature range of integrated circuits up to 300°C has been demonstrated. SOI devices and circuits present advantages in this field over bulk counterparts such as the absence of thermally-activated latch up and reduced leakage current. In this context, various topologies of integrated transmission lines and spiral inductors implemented on standard and high substrate resistivities have been analyzed over a large temperature range. The temperature behavior of the SOI transistors is presented. The main figures-of-merit of the SOI MOSFETs are analyzed and the extraction of the extrinsic and intrinsic parameters of the small signal equivalent circuit is performed. Also, an example of RF circuit applications of the SOI technology, based on a fully integrated Low-Noise Amplifier for low-power and narrow-band applications, is investigated and characterized at high temperature. The main figures-of-merit of the designed circuit are extracted and discussed. The good results show that the SOI technology is now emerging as a good candidate for the realization of analog integrated circuits for low-power and high-temperature applications.