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Attacks on the heap are an increasingly severe threat. State-of-the-art secure dynamic memory allocators can offer protection, however their memory consumption is high, making them suboptimal in many situations. We introduce sys, a secure allocator whose design is driven by memory efficiency. Among other features, sys uses an efficient fine-grain size classes indexing mechanism and implements a novel dynamic canary scheme. It offers a low memory overhead due its size classes optimized for canary usage, its on-demand metadata allocation, and the combination of randomized allocations and over-provisioning into a single memory efficient security feature. sys protects against widespread heap-related attacks such as overflows, over-reads, double/invalid free, and use-after-free. Evaluation over a wide range of applications shows that it offers a significant reduction in memory consumption compared to the state-of-the-art secure allocator (up to 2x in macro-benchmarks), while offering similar or better security guarantees and good performance. / Master of Science / Attacks targeting on the runtime memory (heap allocator) are severe threats to software safety. Statistical results shown that the numbers of heap-related attacks has doubled since 2016. A large number of research works are designed to solve the security problems by offering different techniques to prevent some specific attacks. Not only are they very secure but also fast. However, these secure heap allocators sacrifice the memory usage, all of them at least double the memory consumption. Our work is trying to design and implement a heap allocator, in which it can defend against different attacks, as well as fast and memory-efficient. We carefully re-design some security features in our heap allocator while keep memory-efficient in mind. In the end, we evaluated sys and found that it offers significant reduction on different benchmarks suites. Evaluation also showed that sys can detect a lot of vulnerabilities in the software, while offer the same good performance as the state-of-the-art heap allocator.

We investigated the creation of false memories in the Deese - Roediger - McDermott paradigm. We tested the hypothesis that the false recognition rates will be greater for the critical lures than for unrelated and related distractors. We tested whether there is a direct relationship between semantic relatedness of distractors and their false recognition rates. Our data supported these hypotheses. We concluded that our results support semantic priming and the spreading activation theory, and that the fuzzy-trace theory provides a fitting explanation for our findings. Also, we the measured reaction times of recognition test responses. We tested whether there is a difference in the reaction times of the recognition test responses for true memories, represented by correct recognition of studied words, and false memories, represented by false recognition of nonstudied, critical lures. We tested whether source monitoring plays a significant role in the creation of false memories. Our results showed slower reaction time for false recognition of critical lures than the reaction time for false recognition of nonrelated distractors. This finding suggests that semantic priming and the spreading activation theory alone cannot explain the reaction time data. We concluded that source monitoring is an important factor in creation of false memories in the Deese-Roediger-McDermott paradigm. In addition, we tested whether the reaction time for false recognition of critical lures is greater than reaction time for correct recognition of studied words as would predict the fuzzy-trace theory. Our data support predictions of the fuzzy-trace theory. Our findings suggest that the fuzzy-trace theory provides fitting explanation for the false memory phenomenon.

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Memory and metamemory were examined in 30 hyperactive and 30 nonhyperactive children matched on age, grade, and IQ (as measured by the Vocabulary and the Block Design subtests of the WISC-R), within the context of a broad range of tasks. The five tasks investigated in this study were: (a) a prospective memory task, (b) a feeling-of-knowing task, a visual retention task, (c) a word generation task, (d) and (e) an object span and recall task. Previous research has demonstrated considerable variability in the performance of hyperactive children on memory tasks. They have been shown to perform as well as normal children on tasks of cued recall, paired associates for meaningful words, and on tests of recognition memory. They are distinguished from normal children by their poor performance on tasks of uncued recall, paired associates learning for semantically unrelated words, and in addition, often display performance decrements when task demands increase. The results of this study suggest that hyperactive children are less efficient in metamemory knowledge and skills than normal children. These findings are consistent with the proposal that the difficulties hyperactive children demonstrate on memory tasks may result from a deficiency in their ability to efficiently engage in metamemory processes. The hyperactive children in this study generally had more difficulty than the control children with recall on all the tasks. These included tests of both verbal and nonverbal memory, short and long-term memory, and prospective remembering. Further, they did not derive a memorial benefit, as the control subjects did, when generating their own recall items, or when recalling visual stimuli that could be more easily verbally encoded than others. The hyperactive subjects demonstrated their recall abilities by performing as well as the normal subjects on the recall of read words in the word generation task, and on the recall of the low and medium level of labelability items in the visual retention task. Also, the recall performance of the hyperactive subjects differed significantly between a no-strategy and a provided strategy condition on the prospective memory task. Moreover, there were no group differences on the recognition memory test of the feeling-of-knowing task. The results of this study are consistent with the previous investigations of memory performance in hyperactive children. The present findings further extend the past research by demonstrating selective memory deficits in the hyperactive subjects that are consistent with deficits in metamemory abilities. The proposition that metamemory skills are implicated in the difficulties that the hyperactive children demonstrated in this study is further supported by the difficulty they experienced in describing how they remembered the task items. The hyperactive subjects had more difficulty than the control subjects when attempting to describe a strategy that they used to aid recall. The strategies they described, relative to the control subjects, tended to be vague and poorly defined. These findings suggest that there may be both qualitative and quantitative differences in the way in which hyperactive and normal children use strategies. In summary, the findings of this study suggest that hyperactive children, relative to normal children, seem to be deficient in both their metamemory knowledge and the ability to monitor and control their memory performance. Questions addressing whether these children cannot or do not employ these skills were introduced. The clinical implications of the findings were considered and recommendations were made for future research. / Arts, Faculty of / Psychology, Department of / Graduate

The process of memorization of musical pieces and performing without the support of sheet music is often described as ”playing a piece by heart.” This thesis delves into the process of memorization in classical music, with a particular focus on the author's personal journey in practicing the Kodaly’s solo cello sonata, highlighting the utilization of four distinct memory styles: kinesthetic, aural, visual, and analytical memory. Through an examination of each memory style, this study unravels the multifaceted nature of memorization in musical performance. The thesis not only explores the individual contributions of these memory styles but also examines how to combine them during the learning and memorization process. Through examples, the author sheds light on how she integrated these memory styles, achieving a comprehensive understanding of the piece and ultimately being able to perform it by heart. The findings of this study contribute to the broader field of music cognition, providing valuable insights into the mechanisms involved in memorization and performance. It highlights the importance of considering diverse memory styles and their integration in learning effective memorization techniques in classical music. This study can be useful for musicians who want to develop their memorization process and have a good experience from learning and performing pieces by heart. / <p>Program:</p><p>Zoltán Kodály sonata for unaccompanied cello, Op. 8 </p><p>Medverkande:</p><p>Katariina Kolehmainen - cello</p><p>Den klingande delen är arkiverad. The recording of the concert is filed.</p>

This research was designed to explore autobiographical memory in children, specifically, the personal events involved in memory and memory failures and to what extent children and adults realize what they have forgotten. Since previous research in this domain has focused mainly on adult's or children's ability to recall past events, few have ventured to investigate what underlies the process of forgetting for everyday events in parents and children, and if a link exists between the two. Survey data pertaining to self-reported memory failures along with information on the amount of interaction between parents and children was collected from parents and children at a local elementary school. The results showed that children and parents were more likely to report failure in prospective memory (forgetting to do something) than retrospective memory (forgetting something they already knew). Additionally, when asked what they thought had caused the failure, children were more likely to attribute the lapse to external distractions. Finally, the data showed that the degree of parent-child interaction was significantly related to the detail provided in a child's reported memory failures. The results are discussed in the context of developing a better understanding of, and suggest future avenues for, research in memory and memory failures in children, as well as understanding the relation between parent/child memory.

by Chin-Ming, Cheung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. / Includes bibliographical references (leaves 95-97). / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview --- p.1 / Chapter 1.2 --- Objective --- p.3 / Chapter 1.3 --- Organization of the dissertation --- p.4 / Chapter 2 --- Related Works --- p.6 / Chapter 2.1 --- Previous Cache Works --- p.6 / Chapter 2.2 --- Data Prefetching Techniques --- p.7 / Chapter 2.2.1 --- Hardware Vs Software Assisted --- p.7 / Chapter 2.2.2 --- Non-selective Vs Highly Selective --- p.8 / Chapter 2.2.3 --- Summary on Previous Data Prefetching Schemes --- p.12 / Chapter 3 --- Program Data Mapping --- p.13 / Chapter 3.1 --- Regular and Irregular Data Access --- p.13 / Chapter 3.2 --- Propagation of Data Access Regularity --- p.16 / Chapter 3.2.1 --- Data Access Regularity in High Level Program --- p.17 / Chapter 3.2.2 --- Data Access Regularity in Machine Code --- p.18 / Chapter 3.2.3 --- Data Access Regularity in Memory Address Sequence --- p.20 / Chapter 3.2.4 --- Implication --- p.21 / Chapter 4 --- Register Value Prediction Table (RVPT) --- p.22 / Chapter 4.1 --- Predictability of Register Values --- p.23 / Chapter 4.2 --- Register Value Prediction Table --- p.26 / Chapter 4.3 --- Control Scheme of RVPT --- p.29 / Chapter 4.3.1 --- Details of RVPT Mechanism --- p.29 / Chapter 4.3.2 --- Explanation of the Register Prediction Mechanism --- p.32 / Chapter 4.4 --- Examples of RVPT --- p.35 / Chapter 4.4.1 --- Linear Array Example --- p.35 / Chapter 4.4.2 --- Linked List Example --- p.36 / Chapter 5 --- Program Register Dependency --- p.39 / Chapter 5.1 --- Register Dependency --- p.40 / Chapter 5.2 --- Generalized Concept of Register --- p.44 / Chapter 5.2.1 --- Cyclic Dependent Register(CDR) --- p.44 / Chapter 5.2.2 --- Acyclic Dependent Register(ADR) --- p.46 / Chapter 5.3 --- Program Register Overview --- p.47 / Chapter 6 --- Generalized RVPT Model --- p.49 / Chapter 6.1 --- Level N RVPT Model --- p.49 / Chapter 6.1.1 --- Identification of Level N CDR --- p.51 / Chapter 6.1.2 --- Recording CDR instructions of Level N CDR --- p.53 / Chapter 6.1.3 --- Prediction of Level N CDR --- p.55 / Chapter 6.2 --- Level 2 Register Value Prediction Table --- p.55 / Chapter 6.2.1 --- Level 2 RVPT Structure --- p.56 / Chapter 6.2.2 --- Identification of Level 2 CDR --- p.58 / Chapter 6.2.3 --- Control Scheme of Level 2 RVPT --- p.59 / Chapter 6.2.4 --- Example of Index Array --- p.63 / Chapter 7 --- Performance Evaluation --- p.66 / Chapter 7.1 --- Evaluation Methodology --- p.66 / Chapter 7.1.1 --- Trace-Drive Simulation --- p.66 / Chapter 7.1.2 --- Architectural Method --- p.68 / Chapter 7.1.3 --- Benchmarks and Metrics --- p.70 / Chapter 7.2 --- General Result --- p.75 / Chapter 7.2.1 --- Constant Stride or Regular Data Access Applications --- p.77 / Chapter 7.2.2 --- Non-constant Stride or Irregular Data Access Applications --- p.79 / Chapter 7.3 --- Effect of Design Variations --- p.80 / Chapter 7.3.1 --- Effect of Cache Size --- p.81 / Chapter 7.3.2 --- Effect of Block Size --- p.83 / Chapter 7.3.3 --- Effect of Set Associativity --- p.86 / Chapter 7.4 --- Summary --- p.87 / Chapter 8 --- Conclusion and Future Research --- p.88 / Chapter 8.1 --- Conclusion --- p.88 / Chapter 8.2 --- Future Research --- p.90 / Bibliography --- p.95 / Appendix --- p.98 / Chapter A --- MCPI vs. cache size --- p.98 / Chapter B --- MCPI Reduction Percentage Vs cache size --- p.102 / Chapter C --- MCPI vs. block size --- p.106 / Chapter D --- MCPI Reduction Percentage Vs block size --- p.110 / Chapter E --- MCPI vs. set-associativity --- p.114 / Chapter F --- MCPI Reduction Percentage Vs set-associativity --- p.118

by Sze Siu Ching. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 119-122). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overlapping Computations with Memory Accesses --- p.3 / Chapter 1.2 --- Cache Line Replacement Policies --- p.4 / Chapter 1.3 --- The Rest of This Paper --- p.4 / Chapter 2 --- A Brief Review of IAP Scheme --- p.6 / Chapter 2.1 --- Embedded Hints for Next Data References --- p.6 / Chapter 2.2 --- Instruction Opcode and Addressing Mode Prefetching --- p.8 / Chapter 2.3 --- Chapter Summary --- p.9 / Chapter 3 --- Motivation --- p.11 / Chapter 3.1 --- Chapter Summary --- p.14 / Chapter 4 --- Related Work --- p.15 / Chapter 4.1 --- Existing Replacement Algorithms --- p.16 / Chapter 4.2 --- Placement Policies for Cache Lines --- p.18 / Chapter 4.3 --- Chapter Summary --- p.20 / Chapter 5 --- Replacement and Placement Policies of Prefetched Lines --- p.21 / Chapter 5.1 --- IZ Cache Line Replacement Policy in IAP scheme --- p.22 / Chapter 5.1.1 --- The Instant Zero Scheme --- p.23 / Chapter 5.2 --- Priority Pre-Updating and Victim Cache --- p.27 / Chapter 5.2.1 --- Priority Pre-Updating --- p.27 / Chapter 5.2.2 --- Priority Pre-Updating for Cache --- p.28 / Chapter 5.2.3 --- Victim Cache for Unreferenced Prefetch Lines --- p.28 / Chapter 5.3 --- Prefetch Cache for IAP Lines --- p.31 / Chapter 5.4 --- Chapter Summary --- p.33 / Chapter 6 --- Performance Evaluation --- p.34 / Chapter 6.1 --- Methodology and metrics --- p.34 / Chapter 6.1.1 --- Trace Driven Simulation --- p.35 / Chapter 6.1.2 --- Caching Models --- p.36 / Chapter 6.1.3 --- Simulation Models and Performance Metrics --- p.39 / Chapter 6.2 --- Simulation Results --- p.43 / Chapter 6.2.1 --- General Results --- p.44 / Chapter 6.3 --- Simulation Results of IZ Replacement Policy --- p.49 / Chapter 6.3.1 --- Analysis To IZ Cache Line Replacement Policy --- p.50 / Chapter 6.4 --- Simulation Results for Priority Pre-Updating with Victim Cache --- p.52 / Chapter 6.4.1 --- PPUVC in Cache with IAP Scheme --- p.52 / Chapter 6.4.2 --- PPUVC in prefetch-on-miss Cache --- p.54 / Chapter 6.5 --- Prefetch Cache --- p.57 / Chapter 6.6 --- Chapter Summary --- p.63 / Chapter 7 --- Architecture Without LOAD-AND-STORE Instructions --- p.64 / Chapter 8 --- Conclusion --- p.66 / Chapter A --- CPI Due to Cache Misses --- p.68 / Chapter A.1 --- Varying Cache Size --- p.68 / Chapter A.1.1 --- Instant Zero Replacement Policy --- p.68 / Chapter A.1.2 --- Priority Pre-Updating with Victim Cache --- p.70 / Chapter A.1.3 --- Prefetch Cache --- p.73 / Chapter A.2 --- Varying Cache Line Size --- p.75 / Chapter A.2.1 --- Instant Zero Replacement Policy --- p.75 / Chapter A.2.2 --- Priority Pre-Updating with Victim Cache --- p.77 / Chapter A.2.3 --- Prefetch Cache --- p.80 / Chapter A.3 --- Varying Cache Set Associative --- p.82 / Chapter A.3.1 --- Instant Zero Replacement Policy --- p.82 / Chapter A.3.2 --- Priority Pre-Updating with Victim Cache --- p.84 / Chapter A.3.3 --- Prefetch Cache --- p.87 / Chapter B --- Simulation Results of IZ Replacement Policy --- p.89 / Chapter B.1 --- Memory Delay Time Reduction --- p.89 / Chapter B.1.1 --- Varying Cache Size --- p.89 / Chapter B.1.2 --- Varying Cache Line Size --- p.91 / Chapter B.1.3 --- Varying Cache Set Associative --- p.93 / Chapter C --- Simulation Results of Priority Pre-Updating with Victim Cache --- p.95 / Chapter C.1 --- PPUVC in IAP Scheme --- p.95 / Chapter C.1.1 --- Memory Delay Time Reduction --- p.95 / Chapter C.2 --- PPUVC in Cache with Prefetch-On-Miss Only --- p.101 / Chapter C.2.1 --- Memory Delay Time Reduction --- p.101 / Chapter D --- Simulation Results of Prefetch Cache --- p.107 / Chapter D.1 --- Memory Delay Time Reduction --- p.107 / Chapter D.1.1 --- Varying Cache Size --- p.107 / Chapter D.1.2 --- Varying Cache Line Size --- p.109 / Chapter D.1.3 --- Varying Cache Set Associative --- p.111 / Chapter D.2 --- Results of the Three Replacement Policies --- p.113 / Chapter D.2.1 --- Varying Cache Size --- p.113 / Chapter D.2.2 --- Varying Cache Line Size --- p.115 / Chapter D.2.3 --- Varying Cache Set Associative --- p.117 / Bibliography --- p.119

The capacity for memory is one of the most profound features of the mammalian brain, and the proper encoding and retrieval of information are the processes that form the basis of learning. The goal of this thesis is to further our understanding of the network-level mechanisms supporting learning and memory in the mammalian brain. The hippocampus has been long recognized to play a central role in learning and memory. Although being one of the most extensively studied structures in the brain, the precise circuit mechanisms underlying its function remain elusive. Principal cells in the hippocampus form complex representations of an animal's environment, but in stark contrast to the interneuron population -- and despite the apparent need for functional segregation -- these cells are largely considered a homogeneous population of coding units. Much work, however, has indicated that principal cells throughout the hippocampus, from the input node of the dentate gyrus to the output node of area CA1, differ developmentally, genetically, anatomically, and functionally. By employing in vivo two-photon calcium imaging in awake, behaving mice, we attempted to characterize the role of dened subpopulations of neurons in memory-related behaviors. In the first part of this thesis, we focus on the dentate gyrus input node of the hippocampus. Chapter 2 compares the functional properties of adult-born and mature granule cells. Chapter 3 expands on this work by comparing granule cells with mossy cells, another glutamatergic but relatively understudied cell type. The second part of this thesis focuses on the hippocampal output node, area CA1. In chapter 4, we characterize an inhibitory microcircuit that differentially targets the sublayers of area CA1. And in chapter 5, we directly compare the contributions of these sublayers to episodic and semantic memory.