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In this thesis, next generation low-voltage integrated power semiconductor devices are proposed and analyzed in terms of device structure and layout optimization techniques. Both approaches strive to minimize the power consumption of the output stage in DC-DC converters. In the first part of this thesis, we present a low-voltage CMOS power transistor layout technique, implemented in a 0.25µm, 5 metal layer standard CMOS process. The hybrid waffle (HW) layout was designed to provide an effective trade-off between the width of diagonal source/drain metal and the active device area, allowing more effective optimization between switching and conduction losses. In comparison with conventional layout schemes, the HW layout exhibited a 30% reduction in overall on-resistance with 3.6 times smaller total gate charge for CMOS devices with a current rating of 1A. Integrated DC-DC buck converters using HW output stages were found to have higher efficiencies at switching frequencies beyond multi-MHz. In the second part of the thesis, we present a CMOS-compatible lateral superjunction FINFET (SJ-FINFET) on a SOI platform. One drawback associated with low-voltage SJ devices is that the on-resistance is not only strongly dependent on the drift doping concentration but also on the channel resistance as well. To resolve the issue, a SJ-FINFET structure consisting of a 3D trench gate and SJ drift region was developed to minimize both channel and drift resistances. Several prototype devices were fabricated in a 0.5µm CMOS compatible process with nine masking layers. In comparison with conventional SJ-LDMOSFETs, the fabricated SJ-FINFETs demonstrated approximately 30% improvement in Ron,sp. This is a positive indication that the SJ-FINFET can become a competitive power device for sub-100V rating applications.

In this thesis, next generation low-voltage integrated power semiconductor devices are proposed and analyzed in terms of device structure and layout optimization techniques. Both approaches strive to minimize the power consumption of the output stage in DC-DC converters. In the first part of this thesis, we present a low-voltage CMOS power transistor layout technique, implemented in a 0.25µm, 5 metal layer standard CMOS process. The hybrid waffle (HW) layout was designed to provide an effective trade-off between the width of diagonal source/drain metal and the active device area, allowing more effective optimization between switching and conduction losses. In comparison with conventional layout schemes, the HW layout exhibited a 30% reduction in overall on-resistance with 3.6 times smaller total gate charge for CMOS devices with a current rating of 1A. Integrated DC-DC buck converters using HW output stages were found to have higher efficiencies at switching frequencies beyond multi-MHz. In the second part of the thesis, we present a CMOS-compatible lateral superjunction FINFET (SJ-FINFET) on a SOI platform. One drawback associated with low-voltage SJ devices is that the on-resistance is not only strongly dependent on the drift doping concentration but also on the channel resistance as well. To resolve the issue, a SJ-FINFET structure consisting of a 3D trench gate and SJ drift region was developed to minimize both channel and drift resistances. Several prototype devices were fabricated in a 0.5µm CMOS compatible process with nine masking layers. In comparison with conventional SJ-LDMOSFETs, the fabricated SJ-FINFETs demonstrated approximately 30% improvement in Ron,sp. This is a positive indication that the SJ-FINFET can become a competitive power device for sub-100V rating applications.

Semiconductor technology has already got into nanometer scale. As the dimension keeping scale down, we can get more transistor in the same area, and furthermore the frequency and performance are also enhanced. But nowadays the development of the lithography technology has come to the neck, we must find the other way to improve the performance of transistor. In this study, the strained silicon effect and reliability of CMOS are fully discussed. In order to get strain from the channel, silicon substrate is bent by applying external mechanical stress, the lattice of channel will have strain due to uniaxial tensile stress. By this way, we successfully improve drain current and mobility of NMOS into 12% and 6%, respectively. But there is no variation for PMOS. In addition, by DC stress, we can understand the hot carrier effect to strained silicon. In this work, both NMOS and PMOS present the same result, this is, as the silicon substrate is bent, the sharper of the curve, the worse of the reliability.

Since metal-oxide-semiconductor (MOS) device was first reported around 1959 and utilized for integrated circuits in 1961, complementary MOS technology has become the mainstream of semiconductor industry. Its performance has been improved based on scaling of dimensions of MOS field-effect-transistors (MOSFET) in accordance with Moore’s law, which states that the density of MOSFETs due to scaling approximately doubles every two years. Entering into sub-100nm regime caused a lot of challenges. Traditional way of scaling no longer provided performance enhancement of individual MOSFETs. Increased channel doping which is required to prevent degradation of device electrostatics from short channel effects caused carrier mobility degradation. New inventions needed to be incorporated to sustain performance enhancement trend with scaling. Implementation of process induced strained Si technology allowed mobility enhancement, and high-K/metal gate instead of conventional poly-Si/SiO2 allowed continuing electrical gate oxide thickness scaling, hence extending the life span of Moore’s law. As we are now moving toward 22nm logic technology and below, new concerns have been rapidly aroused. Controlling power consumption and performance variability are becoming as important as developing scaled devices with enhanced performance. Expandability of strained-Si channel technology via process induced strain also faces increasing complexity from ever tighter gate pitch and difficulties in controlling defect level with the channel stress enhancement techniques. At the same time, long-lasting planar MOSFET architecture also faces serious challenges due to the limits of controlling short channel effects. New paradigms and pathways for future technology seems to be required. As a result, new material sets, new device architectures and concepts are being vigorously explored in the literature. These new trends can be categorized into three groups: MOSFET structure with (non-Si) high mobility channel materials, advanced (non-planar) MOSFET structures, and MOSFET-type structures with new device operation concepts such as tunneling FETs. This dissertation presents research on high mobility channel MOSFET structures (planar and non-planar) using group IV material (mainly SiGe) for enhanced performance and reduced operating power. This work especially focuses on improving the performance of short channel device performance of SiGe channel pMOSFETs which has long been researched yet clearly demonstrated in literature only recently. To reach the goal, novel processing technologies such as millisecond flash source/drain anneal and high pressure hydrogen post-metal anneal are explored. Finally, performance dependence on channel and substrate direction has been analyzed to find the optimal use of these SiGe channels. This work describes an exciting opportunity of weighting the possibility of using high mobility channel MOSFETs for future logic technology. / text

Biaxial tensile strained Si grown on SiGe virtual substrates will be incorporated into future generations of CMOS technology due to the lack of performance increase with scaling. Compressively strained Ge-rich alloys with high hole mobilities can also be grown on relaxed SiGe. We review progress in strained Si and dual channel heterostructures, and also introduce high hole mobility digital alloy heterostructures. By optimizing growth conditions and understanding the physics of hole and electron transport in these devices, we have fabricated nearly symmetric mobility p- and n-MOSFETs on a common Si₀.₅Ge₀.₅ virtual substrate. / Singapore-MIT Alliance (SMA)

In this thesis, we investigate the electrical properties and reliability of novel metal-oxide-semiconductor field-effect transistors (MOSFETs) for 65 nm technology node and below. Roughly, we divide the thesis into two parts, strained-silicon channel engineering and high-k/metal gate stacks respectively. Firstly, to study the influence of stress on carrier transport properties, we proposed an approach to get uniaxial compressive/tensile stress from the channel by bending silicon substrate to enhance device performance. By applying uniaxial longitudinal tensile/compressive stress, the drain current and mobility were found to increase obviously in n/p-type MOSFETs, respectively. The enhancement can be attributed to the reduction of effective transport mass and to the suppression of inter-valley scattering. However, we found that the external mechanical stress aggravated hot carrier effects in n-type MOSFETs. Therefore, in n-type MOSFETs, the behaviors of the substrate current and the impact ionization rate under mechanical stress are investigated. It was found that the substrate current and gate voltage corresponding to the maximum impact ionization current has significantly increased by increasing external mechanical stress. According to the relationship to the strain-induced mobility enhancement, the increase in impact ionization efficiency resulted from the decrease in threshold energy for impact ionization which was due to the narrowing of the band gap. In p-type MOSFETs, the reliability issue, named negative bias temperature instability, is the dominant degradation mechanism during ON-state operation. Therefore, we investigate the NBTI characteristics of strained p-type MOSFETs with external uniaxial tensile/compressive stress. The results indicate that uniaxial compressive stress not only enhances drive current but also reduces NBTI degradation. On the contrary, uniaxial tensile stress leads to a significant degradation in both of drive current and NBTI behavior. The observed Cgc-Vg curve shows the inversion capacitance is strongly dependent on mechanical strain, meaning that the probability of electrochemical reaction decreases/or increases due to the changes in inversion carrier density according to the Nit generation rate of the reaction-diffusion model. Moreover, the charge pumping result is also consistent with the threshold voltage shift of the strained device, which means the degradation is mainly due to trap generation at the Si/SiO2 interface. In addition, to investigate the influences of biaxial compressive stress on p-MOSFETs, we attempts to combine intrinsic and external mechanical stress. It was found that drain current and hole mobility of p-type MOSFET with Si1-xGex raised Source/Drain and external applied mechanical stress significantly decreased due to the increase of effective conductive mass at room temperature. However, this phenomenon was inverted above 363K. Because hole can gain enough thermal energy to transit to higher energy level by inter-valley scattering, its transport mechanism was dominated by lower effective mass at higher energy level. Besides, the model is also evidenced that the mobility degradation under biaxial compressive stress becomes aggravated while temperature decreases from 300 K to 100 K, which is mainly due to the increase of the ratio of carriers occupied in lowest band. On the other hand, the SiO2 dielectric and poly-gate are unsuitable for CMOS application below 65 nm technology node due to unacceptable gate leakage current. Therefore, in the second section of this thesis, we established the electrical characteristics and physical mechanisms of MOSFETs with HfO2 dielectric/TiN gate by analyzing experimental data from charge pumping, split C-V, DC Id-Vg, and pulse Id-Vg. It is found that the threshold voltage (Vth) has a significant decrease as titanium increases in metal gate for n-MOSFETs, whereas the Vth increases in p-MOSFETs. By examining flat band voltage, we found the Vth shift was resulted from metal gate work function (£pm) which became smaller as titanium increased in metal gate. In addition,the dependence of effective mobility on temperature from 100K to 300K was entirely analyzed, which indicated HfO2 remote phonon scattering as the dominant cause of the mobility degradation in n- and p-type MOSFETs when titanium decreased. However, the gate leakage current is also strongly dependent on the nitrogen in metal gate. It is proved that the nitrogen can assivate the traps in HfO2 by pulse I-V,leading to the decrease in gate leakage dominated by Frenkel- Poole mechanism.

Electronic devices such as high power devices, microprocessors and memories in integrated circuit are primarily composed of metal-oxide-semiconductor field effect transistors (MOSFETs), due to the advantages of low cost, low power consumption and easy to scale down. However, the aggressively scaled conventional MOS devices have suffered remarkable short channel effects such as drain induced barrier lowering, punch-through, and direct-tunneling gate leakage. These problems not only lower the gate controllability but also increase the standby power consumption. Because the SiO2 dielectric and poly-gate are improper for CMOS application below 45 nm technology node due to the critical gate leakage current. Therefore, we investigate the electrical characteristics and physical mechanisms of MOSFETs with HfO2/TixN1-x gate stacks by using split C-V, pulsed Id-Vg, and charge-pumping techniques. The experimental results indicate that dynamic stress is more serious than static stress, and hot-carrier effect corresponding to different gate stress biases demonstrate distinct dominant degradation behaviors and the charge-trapping phenomenon. Furthermore, different concentration of titanium in TiN metal gate significantly affect device characteristics associated with the amount of nitrogen diffusion from the metal gate to high-k bulk and the SiO2/Si interface layer.

For the high performance integrated circuits applications such as microprocessors, memories and high power devices, the metal-oxide-semiconductor field effect transistors (MOSFETs) is the most important device due to its low cost, power consumption and scalable property especially. However, the aggressive scaling of conventional MOS devices suffered from noticeable short channel effects such as drain induction barrier lower, punch through, and direct tunneling gate leakage. Those problems not only lower the gate control ability but also increase the standby power consumption. For future VLSI devises below 65 nm regimes, silicon-on-insulator (SOI) and high-k/metal gate MOSFETs are considered to be possible candidates because of faster operation speed and lower power consumption. Therefore, this dissertation investigates the electrical characteristics and reliability issues of novel MOSFETs for 65 nm and below technology. It is roughly divided into two parts, partially depleted (PD) SOI MOSFETs and high-k/metal gate stack MOSFETs, respectively. In the first part, we systematically investigate the mechanism of gate-induced floating body effect (GIFBE) for advanced PD SOI n-MOSFETs. Based on different operation conditions, it was found that the dominant mechanism can be attributed to the anode hole injection (AHI) rather than the widely accepted mechanism of electron-valence band (EVB) tunneling. Analyzing the GIFBE in different temperature provides further evidence that the accumulation of holes in the body results from the AHI induced direct tunneling current from the poly-Si gate. In addition, we proposed an approach by bending silicon substrate to further study the impact of mechanical strain on GIFBE. The experimental result indicates that the strain effect indeed decreases the gate leakage current, but increases the hole-valence band (HVB) tunneling current, which indicates that GIFBE becomes serious under mechanical strain. Based on our proposed AHI model, this phenomenon can be mainly due to strain-induced band gap narrowing in the poly-Si gate. In p-type MOSFETs, the reliability issue, named negative bias temperature instability (NBTI), is the dominant degradation mechanism during ON-state operation. Therefore, we also investigate the GIFBE on NBTI degradation for PD SOI p-MOSFETs. The experimental results indicate GIFBE causes a reduction in the electrical oxide field, leading to an underestimate of NBTI degradation. This can be partially attributed to the electrons tunneling from the process-induced partial n+ poly gate. However, based on different operation conditions, we found the dominant origin of electrons was strongly dependent on holes in the inversion layer under source/drain grounding. Therefore, we propose the anode electron injection (AEI) model, similar to anode hole injection model, to explain how this main electron origin is generated during the NBTI stress. Finally, based on our proposed model, we further study influence of mechanical strain on GIFBE for SOI p-MOSFETs. On the other hand, the SiO2 dielectric and poly-gate are unsuitable for CMOS application below 45 nm technology node due to unacceptable gate leakage current. Therefore, in the second part of this thesis, we investigate the electrical characteristics and physical mechanisms for MOSFETs with HfO2/TixN1-x stacks by using split C-V, DC Id-Vg, and charge pumping techniques. The experimental results indicates that different ratio of Ti strongly affect various parameters, including threshold voltage, mobility, and subthreshold swing, respectively. In addition, the gate leakage current is also strongly dependent on the nitrogen in metal gate. By charge pumping technique, it was found that with increasing Ti concentration of metal gate, there is a trade-off relationship among the interface traps and bulk defects of high-k dielectric. This phenomenon is associated with the amount of nitride diffusion from the metal gate to high-k bulk and SiO2/Si interface layer. In the aspects of reliability, charge trapping in high-k gate stacks remains an important issue since it causes the threshold voltage (Vth) shift and drive current degradation. This phenomenon can be attributed to a large number of pre-existing traps in the high-k dielectric layer. In real circuit operation, the devices are generally operated in the dynamic condition. Therefore, the following study further investigates Vth instability of Hf-based n-MOSFETs under the dynamic bias operation. The static condition was also performed on the identical device for a comparison. The results indicate threshold voltage (Vth) instability under dynamic stress is more serious than that under static stress, owning to transient charge trapping within high-k dielectric. In addition, the Vth shift clearly increases with an increase in dynamic stress operation frequency. According to these experimental results, we propose a possible physical model for electron trapping phenomena under dynamic stress. Based on our proposed model, we further dynamic stress induced charge trapping characteristics for devices with different Ti1-xNx composition of metal-gate electrodes. In addition, we further respectively investigates the temperature dependence of dynamic positive bias stress (PBS) and negative bias stress (NBS) degradation in n-type and p-type MOSFETs with high-k/metal gate stacks. The experimental results indicate there is a contrary trend in temperature dependence of Vth shifts for n- and p-MOSFETs under dynamic PBS and NBS, respectively. The Vth shift decreases with increasing temperature for n-MOSFETs under dynamic PBS. This is due to the thermal emission of trapped electrons in high temperature, leading to the reduction in. A contrary trend with temperature for p-MOSFETs under dynamic NBS can be attributed to the interface trap generation induced by NBTI. On the other hand, hot carrier effect in high-k/metal gate n-MOSFETs was still one of major device reliability concern in device scaling. However, the stress-induced drain leakage current degradation in device with high-k/metal gate stacks has not received as much attention. In fact, the GIDL behavior is associated with phenomenon of charge trapping in high-k dielectric layer. Therefore, the final study is to investigate the effects of channel hot carrier stress (CHCS) on the gate-induced drain leakage current (GIDL) for n-MOSFETs with HfO2/Ti1-xNx gate stacks. It was found that the behavior of GIDL current during CHCS has dependence with the interfacial layer (IL) oxide thickness of high-k/metal gate stacks. As IL thickness becomes thinner, the GIDL current has a gradual decrease during CHCS, which is contrary to the result of thick-oxide IL devices. Based on the variation of GIDL current in different stress voltage across gate and drain terminals, trap-assisted band to band holes injection model was proposed to explain the different behavior of GIDL current for different IL thickness. Furthermore, we also investigated the impact of different Ti1-xNx composition of metal gate electrode on the IGIDL after CHCS, and observed that the magnitude of IGIDL decreases with the increase of nitride ratio. This is due to the fact that nitride atoms diffusing from the metal gate fill up oxygen vacancies, and reduce the concentration of traps in high-k dielectric.

As semiconductor device sizes continue to decrease, the traditional bulk CMOS technology is seen as an obstacle itself by the physical device limitations. One of the physical limitations of MOSFETs is to ensure that the SCEs and related issues can be controlled to maintain device performance targets. For SOI MOSFETs, due to the presence of BOX, short-channel behavior is improved, as compared to bulk Si. But self-heating plays a key role in affecting device reliability. Thus, these challenges make the future of planar technology being difficult to be continuously implemented. In this thesis we introduce the concept of the isolation-last process which moves the ¡§FET active region definition¡¨ to the back of the S/D activation process. There are two kinds of devices to be fabricated: BOSDT-APSB MOSFET and ZBOSDT-APSB MOSFET. BOSDT is the acronym of block-oxide S/D-tie and APSB is the acronym of additional poly-Si body. It should be noted that the ZBO is the acronym of zero BO (absence of BO). Actually, the two above-mentioned devices can be referred to as the poly-Si TFTs, due to the presence of poly-Si active region. However, for the ultimate scaling, the two proposed devices can have an additional silicon body or ASB. Two proposed devices, being a consideration of fabrication aspects, have a different design compared to their scaled-down sizes. But we can still hold the ASB¡¦s core values. According to the simulation, the ASB shows its ability to alleviate the SCEs and offers improved cooling capability, which is because the additional body provides extra space for heat dissipation. The unwanted results are that the large gate leakage current and parasitic capacitances are observed as the ASB is created. Fortunately, these results are still within acceptable limits. Experimental results show that the APSB is desirable to suppress the SCEs in both BOSDT and ZBOSDT MOSFETs. We also verify that the device¡¦s cooling capability can be improved by introducing an APSB into MOSFETs. In other words, the APSB is useful for enhanced performance and reliability, although some disadvantages exist also. The BO has been proven to have a better channel controllability than its counterpart. But the ZBO can be seen as the ultimately scaled BO. And after scaling, the schemes of ZBO and ASB become more pronounced.