This work focuses on device design and process integration of high-performance Ge-based devices for CMOS applications and beyond. Here we addressed several key challenges towards Ge-based devices, such as, poor passivation, underperformance of nMOSFETs, and incompatibility of fragile Ge wafers for mass production. We simultaneously addressed the issues of bulk Ge and passivation for pMOSFETs, by fabricating Si-capped epitaxial Ge:C(C<0.5%) devices. Carbon improves the crystalline quality of the channel, while Si capping prevents GeOx formation, creates a quantum well for holes and thus improves mobility. Temperature-dependent characterization of these devices suggests that Si cap thickness needs to be optimized to ensure highest mobility. We developed a simple approach to grow GeO₂ by rapid thermal oxidation, which provides improved passivation, especially for nMOSFETs. The MOSCAPs with GeO₂ passivation show ~10× lower Dit (~8×10¹¹ cm⁻²eV⁻¹) than that of the HF-last devices. The Ge (111) nMOSFETs with GeO₂ passivation show ~2× enhancement in mobility (~715 cm²V⁻¹s⁻¹ at peak) and ~1.6× enhancement in drive current over control Si (100) devices. For improved n⁺/p junctions, we proposed a simple technique of rapid thermal diffusion from "spin-on-dopants" to avoid implantation damage during junction formation. These junctions show a high ION/IOFF ratio (~10⁵⁻⁶) and an ideality factor of ~1.03, indicating a low defect density, whereas, ion-implanted junctions show higher Ioff (by ~1-2 orders) and a larger ideality factor (~1.45). Diffusion-doped and GeO₂-passivated Ge(100) nMOSFETs show a high ION/IOFF ratio (~10⁴⁻⁵) , a low SS (111 mV/decade), and a high [mu]eff (679 cm²V⁻¹s⁻¹ at peak). Moreover, diffusion-doped Ge (111) nMOSFETs show even higher [mu]eff (970 cm²V⁻¹s⁻¹ at peak) that surpasses the universal Si mobility at low Eeff. For Beyond CMOS devices, we investigated Mn-doped Ge:C-on-Si (100), a novel Si-compatible ferromagnetic semiconductor. The investigation suggests that the magnetic properties of these films depend strongly on crystalline structure and Mn concentration. On a different approach, we developed LaOx/SiOx barrier for Spin-diodes that reduces contact resistance by ~10⁴, compared to Al₂O₃ controls and hence is more conducive for spin injection. These ferromagnetic materials and devices can potentially be useful for novel spintronic devices. / text

For patients receiving radiation therapy, there is a risk of developing radiation induced carcinomas, especially if they have a long life expectancy. However, radiotherapy is not the only contributor of radiation exposure to healthy tissue. With the introduction of highly conformal treatment techniques comes the increase in pretreatment imaging necessary to accurately target tumour volumes and consequently, radiation exposure to healthy tissue. In this work the radiation dose delivered to radiosensitive organs from a number of treatment planning techniques was evaluated and the risk of radiation induced cancer was assessed. MOSFET detectors and Gafchromic film were used to measure the accumulative concomitant dose to the thyroid and contralateral breast from early stage breast carcinoma radiotherapy and to the contralateral testis from seminoma radiotherapy, with dose contributions from CT imaging for treatment planning, pretreatment imaging (CBCT) and treatment delivery peripheral dose. To the author's knowledge this is the first work investigating the total concomitant treatment related dose and associated risk to these treatment sites. Peripheral dose contributed the largest concomitant dose to the healthy tissue, measuring up to 0.7, 1.0 and 5.0 Gy to the testis, thyroid and contralateral breast, respectively. The highest testicular, thyroid and contralateral breast carcinoma risk was found to be 0.4, 0.2 and 1.4%, respectively. In conclusion, the risk of radiation induced carcinoma to the assessed radiosensitive tissues was found to be minimal, however, when considering treatment techniques and/or introducing pretreatment imaging protocols, the dose to the normal tissue should be kept as low as reasonably achievable.

Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally efficient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, efficient compact models for these new transistors are required for their successful utilization in integrated circuits. Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational efficiency at the same level. Such effort aims to generalize the compact model and also to capture the oxide thickness asymmetry effect, which might prevail in practical devices due to process uncertainties and thus affects the device performance significantly. However solution to this modeling problem is nontrivial due to the bias-dependent asym-metric nature of the electrostatic. Using the single implicit equation based Poisson so-lution and the unique quasi-linear relationship between the surface potentials, previous researchers of our laboratory have reported the core model for such asymmetric CDG MOSFET. In this work effort has been put to include Non-Quasistatic (NQS) effects, different small-geometry effects, and noise model to this core, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry effects. This property of the device along with some other new techniques are used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully imple-mented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.

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The SiC MOSFET has attracted interest due to its superior characteristics compared to its Si counterpart. Several SiC MOSFETs are usually paralleled to increase current capability, considering cost effectiveness and manufacturability. Current unbalance among the MOSFETs is a concern as it affects reliability. The two main causes are asymmetrical layout and parameter mismatch. The variation in parameters, unlike circuit or module layout, is unavoidable during production. Among all the parameters of MOSFET, the spreads in on-state resistance (Rds(on)) and threshold voltage (Vth) are the major concerns during paralleling. The disparity in Rds(on) causes static current unbalance which is self-limited due to the positive temperature coefficient of Rds(on). Its influence is not investigated here. The threshold voltage Vth has a negative temperature coefficient, forcing the MOSFET with lower Vth to carry more current during switching transient. Paralleled MOSFETs are usually de-rated to guarantee safe operation. Balancing of peak currents during switching transient isthe goal of this work. Integration of current/voltage sensors into paralleled structure is difficult in real application. Complicated feedback loop design and separate gate drivers also need to be avoided in perspective of cost and volume. Passive balancing solutions are investigated in this dissertation. The inductors and resistors most effective in improving current sharing are identified by parametric analysis. Their current balancing mechanisms are analyzed in circuit point of view. The design guidelines involving the magnitude of Vth mismatch, current rise time, and unbalance percentage are derived for the selection of passive components. The theory upholds well when substantial parasitics from device package and layout exist. Several passive balancing structures are analyzed and compared in terms of current balancing capability, voltage stress, total switching loss, and switching loss difference. All of them can provide much better current and power balancing without increasing switching loss. Some of the them may increase the stress-inducing inductance, which can be reduced by negative magnetic coupling. Perfect coupling between power-source inductors would enable current matching without penalty on voltage stress. Common-source inductance (Lcm) is effective in dynamic balancing, but at the expense of higher switching loss. It is not considered in power module application because Kelvin connection is normally applied. However, wire bond inside the package of discrete MOSFETs and part of the external leads are inevitable and add to Lcm. Peak-current and switching energy mismatches vary with operating conditions (including input voltage, input current, and switching speed). Design guidelines and procedures that are valid for wide operating range are provided for cases with and without Lcm. This dissertation also models the switching energy and switching energy mismatch of paralleled MOSFETs. The influence of operating conditions, passive balancing components, layout and package parasitic inductances, nonlinear channel performance, and voltage dependent parasitic capacitors are included in the modeling process. The resulting high order system is simplified by reducing the number of passive components and number of devices without losing accuracy. The influence of current balancing components and magnitude of threshold voltage mismatch on sharing are discussed based on modeling results. In conclusion, this dissertation balances the transient currents between paralleled SiC MOSFETs automatically by inductance, resistance and magnetic coupling. This procedure is done utilizing one gate driver without current/voltage sensors and feedback loop. Those solutions work for both polarities of Vth mismatch and force balancing from the first current peak. Design guidelines involving the magnitude of Vth mismatch, current rise time, and maximum peak-current difference are derived to guide the choice of passive components. The detail design procedures are recommended to force currents to share over wide operating range. The aforementioned benefits are demonstrated by two paralleled SiC MOSFETs (C2M0160120D) tested at variant operating conditions. The difference of peak currents can be reduced below 5% of steady-state current in every switching transient. Switching energy mismatch percentage can be reduced by 6 times without increasing total switching energy. / Ph. D.

Les MOSFETs ultra-thin body UTB ont été fabriqués avec une technologie auto-alignée. Le canal conducteur est constitué d’InGaAs à 75% de taux d’indium ou d’un composite InAs/In0,53Ga0,47As. Une fine couche d'InP (3 nm) a été insérée entre le canal et l'oxyde, afin d’éloigner les défauts de l’interface oxyde-semiconducteur du canal. Enfin, une épaisseur de 4 nm d'oxyde de grille (Al2O3) a été déposée par la technique de dépôt des couches atomiques. Les contacts ohmiques impactent les performances des MOSFETs. La technologie UTB permet difficilement d’obtenir des contacts S/D de faibles résistances. De plus, l’utilisation de la technique d’implantation ionique pour les architectures UTB est incompatible avec le faible budget thermique des matériaux III-V et ne permet pas d’obtenir des contacts ohmiques de bonne qualité. Par conséquent, nous avons développé une technologie auto-alignée, basée sur la diffusion du Nickel « silicide-like » par capillarité à basse température de recuit (250°C) pour la définition des contacts de S/D. Finalement, nous avons étudié et analysé la résistance de l'alliage entre le Nickel et les III-V. A partir de cette technologie, des MOSFET In0,75Ga0,25As et InAs/In0,53Ga0,47As ont été fabriqués. On constate peu de différences sur les performances électriques de ces deux composants. Pour le MOSFET InAs/InGaAs ayant une longueur de grille LG =150 nm, un courant maximal de drain ID=730 mA/mm, et une transconductance extrinsèque maximale GM, MAX = 500 mS/mm ont été obtenu. Le dispositif fabriqué présente une fréquence de coupure fT égale à 100 GHz, et une fréquence d'oscillation maximale fmax de 60 GHz, pour la tension drain-source de 0,7 V. / Abstract : Silicon-based devices dominate the semiconductor industry because of the low cost of this material, its technology availability and maturity. However, silicon has physical limitations, in terms of mobility and saturation velocity of the carriers, which limit its use in the high frequency applications and low supply voltage i.e. power consumption, in CMOS technology. Therefore, III-V materials like InGaAs and InAs are good candidates because of the excellent electron mobility of bulk materials (from 5000 to 40.000 cm2 /V.s) and the high electron saturation velocity. We have fabricated ultra-thin body (UTB) InAs/InGaAs MOSFET with gate length of 150 nm. The frequency response and ON-current of the presented MOSFETs is measured and found to have comparable performances to the existing state of the art MOSFETs as reported by the other research groups. The UTB MOSFETs were fabricated by self-aligned method. Two thin body conduction channels were explored, In0,75Ga0,25As and a composite InAs/In0,53Ga0,47As. A thin upper barrier layer consisting of InP (3nm) is inserted between the channel and the oxide layers to realized a buried channel. Finally, the Al2O3 (4 nm) was deposited by the atomic layer deposition (ALD) technique. It is well known that the source and drain (S/D) contact resistances of InAs MOSFETs influence the devices performances. Therefore, in our ultra-thin body (UTB) InAs MOSFETs design, we have engineered the contacts to achieve good ohmic contact resistances. Indeed, for this UTB architecture the use of ion implantation technique is incompatible with a low thermal budget and cannot allow to obtain low resistive contacts. To overcome this limitation, an adapted technological approach to define ohmic contacts is presented. To that end, we chose low thermal budget (250°C) silicide-like technology based on Nickel metal. Finally, we have studied and analyzed the resistance of the alloy between Nickel and III-V (Rsheet). MOSFET with two different epilayer structures (In0,75Ga0,25As and a composite InAs/In0,53Ga0,47As) were fabricated with a gate length (LG) of 150 nm. There were few difference of electrical performance of these two devices. We obtained a maximum drain current (ION) of 730 mA/mm, and the extrinsic transconductance (GM, MAX) showed a peak value of 500 mS/mm. The devices exhibited a current gain cutoff frequency fT of 100 GHz and maximum oscillation frequency fmax of 60 GHz for drain to source voltage (VDS) of 0.7 V.

Ce travail vise à étudier la robustesse de trois générations de MOSFET SiC de puissance (Silicon Carbide Metal Oxide Semiconductor Field E_ect Transistors). Plusieurs approches sont suivies : la caractérisation électrique, la modélisation physique, les tests de vieillissement et la simulation physique. Un modèle compact basé sur une nouvelle méthode d'extraction de paramètres et sur les résultats de caractérisation électrique est présenté. Les paramètres extraits du modèle (tensionde seuil, transconductance de la région de saturation et paramètre du champ électrique transverse) sont utilisés pour analyser avec précision le comportement statique de trois générations de MOSFET SiC. La robustesse de ces dispositifs sont étudiées par deux tests : le test HTRB (High Temperature Reverse Bias) et le test ESD (Electrostatic Discharge). Une simulation physique est réalisée pour comprendre l'impact de la température et des paramètres physiques sur les caractérisations électriques des MOSFETs SiC. / This work aims to investigate the robustness of three generations of power SiC MOSFETs (SiliconCarbide Metal Oxide Semiconductor Field E_ect Transistors). Several approaches are followed :electrical characterization, device modeling, ageing tests and physical simulation. An improvedcompact model based on an accurate parameters extraction method and one electrical characterization results is presented. The parameters extracted precisely from the model (thresholdvoltage, saturation region transconductance...) are used to accurately analyze the static behaviorof two generations of SiC MOSFETs. The robustness of these devices are investigated bytwo tests : HTRB (High Temperature Reverse Bias) stress and an ESD (Electrostatic Discharge)stress. Physical simulation is conducted to understand the impact of the temperature and thephysical parameters on the device electrical characterizations.

Mass spectrometry has long been used as a scientific tool in a wide variety of applications. A portable mass spectrometer would make many of these applications faster and more efficient. One of the key components of a mass spectrometer is its ion detection system; to make a mass spectrometer portable, this system must be small and involve as few components as possible. Single ion detection has been achieved through several methods, nearly all of which are well-known and understood. These methods, however, often require bulky vacuum and/or cooling systems in order to achieve high sensitivity. An ion detection system that can achieve high sensitivity under atmospheric pressure and normal temperature conditions would make portable mass spectrometry much more feasible. This thesis introduces a new method of detecting ions which does not require a vacuum or cold temperatures to operate: the solid-state ion detector, or SSID. Although ion detection using solid-state devices has been investigated previously, this work introduces metal-oxide-semiconductor field-effect transistors (MOSFETs) in a cascode configuration which acts as the primary detector when combined with a Faraday cup and mechanical switch. This detector is followed by a second amplifying stage which features RC-filters to help reduce noise and improve the detector's overall sensitivity. The detector is placed on a printed circuit board that was designed to fit a pre-determined system. Additional power circuitry for the mechanical switch was also designed and added to the detector circuitry. The SSID will be most sensitive when the input capacitance is made as small as possible. With this in mind, MOSFETs with a very low (< 1pF) gate capacitance were fabricated at BYU for use in the SSID. The performance of these MOSFETs was compared to a commercially available device in the same configuration. When tested, both MOSFETs had a sensitivity of hundreds of electrons when integrated in the complete SSID circuit. The commercial MOSFET demonstrated an estimated sensitivity of 150 electrons. The SSID shows much promise, and suggestions are made for further improving it to achieve even higher sensitivity levels. If made more sensitive, the next step would be to create an array of SSID detectors to be used in a portable mass spectrometer.

This thesis presents the theoretical and experimental framework for the development of accurate on-wafer S-parameter and noise parameter measurements of silicon devices in the upper millimetre-wave frequency range between 70 GHz and 300 GHz. Novel integrated noise parameter test setups were developed for nanoscale MOSFETs and SiGe HBTs and validated up to 170 GHz. In the absence of accurate foundry models in this frequency range, the experimental findings of this thesis have been employed by other graduate students to design the first noise and input impedance matched W- and D-band low-noise amplifiers in nanoscale CMOS and SiGe BiCMOS technologies. The results of the D-band S-parameter characterization techniques and of the new Y-parameter based noise model have been used by STMicroelectronics to optimize the SiGe HBT structure for applications in the D-band. In the first half of the thesis, theoretical analysis indicates that, for current silicon devices, distributive effects in test structure parasitics will become significant only beyond 300 GHz. This conclusion is supported by experiments which compare the lumped-element based open-short and the transmission line based split-thru de-embedding techniques to the multiline thru-reflect-line (TRL) network analyzer calibration algorithm. Electromagnetic simulations and measurements up to 170 GHz demonstrate that, for microstrip transmission lines with metal ground plane placed above the silicon substrate, the line capacitance per unit length remains a weak function of frequency. Based on this observation, the multiline TRL algorithm has been modified to include a dummy short de-embedding structure. This allowed for the first time to perform single step calibration and de-embedding of silicon devices using on-silicon calibration standards. The usefulness of the proposed method was demonstrated on the extraction of the difficult-to-measure SiGe HBT and nanoscale MOSFET model parameters, including transcondutance delay, tau, gate resistance, source resistance, drain-source capacitance, and channel resistance, Ri. Building on the small-signal characterization technique developed in the first half, a new Y-parameter based noise model for SiGe HBTs, that includes the correlation between the base and collector shot noise currents, is proposed in the second half of the thesis along with a method to extract the noise transit time parameter. With this model, the high frequency noise parameters of a SiGe HBT can be calculated from the measured Y-parameters, without requiring any noise figure measurements. Finally, to validate the proposed noise model, the first on-wafer integrated noise parameter measurement systems were designed and measured in the W- and D-bands. The systems enable millimetre-wave noise parameter measurements with the multi-impedance method by integrating the impedance tuner and an entire millimetre-wave noise receiver on the same die as the device-under-test. Good agreement was obtained between the noise parameters calculated from the Y-parameter measurements and those obtained from direct noise figure measurements with the integrated systems. The results indicate that the minimum noise figure of state-of-the-art advanced SiGe HBTs remains below 5 dB throughout the D-band, making them suitable for a variety of commercial products in this frequency range.