Efficient handoff algorithms cost-effectively enhance the capacity and Quality of Service (QoS) of cellular systems. This research presents novel approaches for the design of high performance handoff algorithms that exploit attractive features of several existing algorithms, provide adaptation to dynamic cellular environment, and allow systematic tradeoffs among different system characteristics. A comprehensive foundation of handoff and related issues of cellular communications is given. The tools of artificial intelligence utilized in this research, neural networks and fuzzy logic, are introduced. The scope of existing simulation models for macrocellular and microcellular handoff algorithms is enhanced by incorporating several important features. New simulation models suitable for performance evaluation of soft handoff algorithms and overlay handoff algorithms are developed. Four basic approaches for the development of high performance algorithms are proposed and are based on fuzzy logic, neural networks, unified handoff candidate selection, and pattern classification. The fuzzy logic based approach allows an organized tuning of the handoff parameters to provide a balanced tradeoff among different system characteristics. The neural network based approach suggests neural encoding of the fuzzy logic systems to simultaneously achieve the goals of high performance and reduced complexity. The unified candidacy based approach recommends the use of a unified handoff candidate selection criterion to select the best handoff candidate under given constraints. The pattern classification based approach exploits the capability of fuzzy logic and neural networks to obtain an efficient architecture of an adaptive handoff algorithm. New algorithms suitable for microcellular systems, overlay systems, and systems employing soft handoff are described. A basic adaptive algorithm suitable for a microcellular environment is proposed. Adaptation to traffic, interference, and mobility has been superimposed on the basic generic algorithm to develop another microcellular algorithm. An adaptive overlay handoff algorithm that allows a systematic balance among the design parameters of an overlay system is proposed. Important considerations for soft handoff are discussed, and adaptation mechanisms for new soft handoff algorithms are developed. / Ph. D.

"L’industrie nano repousse constamment les limites de la miniaturisation. Pour les systèmes CMOS à mémoires non-volatiles, des phénomènes qui étaient négligeables autrefois sont à présent incontournables et nécessitent des modèles de plus en plus complexes pour décrire, analyser et prédire le comportement électrique de ces dispositifs.Le but de cette thèse est de répondre aux besoins de l’industriel, afin d’optimiser au mieux les performances des produits avant et après les étapes de production. Cette étude propose des solutions, comme des méthodes de test innovantes pour des technologies telles que les mémoires non-volatiles EEPROM embarquées.La première méthode proposée, consiste à extraire la densité de pièges (NiT) générée, au cours du cyclage, dans l’oxyde tunnel de cellules EEPROM, à partir d’une Macro cellule de test reprenant toutes les caractéristiques d’un produit fini. Les résultats expérimentaux sont ensuite injectés dans un modèle analytique décrivant le phénomène de SILC (Stress Induced Leakage Current) qui est le principal effet issu de ces pièges. La densité de pièges en fonction du nombre de cycles est ensuite extraite par interpolation entre les courbes expérimentales et les courbes simulées par le modèleLa seconde méthode propose une étude de corrélation statistique entre le test traditionnel de mise en rétention et le test de stress électrique aux bornes de l’oxyde tunnel, proposant des temps d’exécution bien plus courts. Cette étude se base sur les populations de cellules défaillantes à l’issue des deux tests. C’est en comparant les distributions sur ces populations qu’une loi de corrélation apparaît sur la tendance comportementale des cellules." / The nano industry constantly extends the size limits, especially for CMOS devices with embedded non-volatile memories. Each size reduction step always induces new challenges caused by phenomenon which were previously negligible. As a result, more complex models are required to describe, analyze and predict as well as possible the electrical behaviors. The main goal of this thesis is to propose solutions to the industry in term of test, to optimize the performances before and after the whole process steps. Thus, this study proposes two innovative methodologies dedicated to embedded non-volatile EEPROM memories based devices.The first of them consists in to extract the post-cycling generated tunnel oxide traps density (NiT), directly from a macro cell. The experimental results are then used to be compared with an analytical model calculation which perfectly describes the Stress Induced Current phenomena (SILC). This electrical current directly comes from the generated traps inside the cells tunnel oxide. An interpolation is then done between the model and the experimental resulting curves, to extract the tunnel oxide traps density.The second study proposes a method of statistical correlation between the traditional retention test and testing of electrical stress across the tunnel oxide which has shorter execution time. This study is based on cell populations after failing both tests. By comparing the distributions of these populations a correlation law appears between the cells behavioral tendencies. Following this study the replacement of long retention tests by shorter electrical stress tests may be considered.