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Doctor of Philosophy / Department of Chemical Engineering / James H. Edgar / The integration of high-κ dielectrics with silicon and III-V semiconductors is important due to the need for high speed and high power electronic devices. The purpose of this research was to find the best conditions for fabricating high-κ dielectrics (oxides) on GaN or Si. In particular high-κ oxides can sustain the high breakdown electric field of GaN and utilize the excellent properties of GaN. This research developed an understanding of how process conditions impact the properties of high-κ dielectric on Si and GaN. Thermal and plasma-assisted atomic layer deposition (ALD) was employed to deposit TiO₂ on Si and Al₂O₃ on polar (c-plane) GaN at optimized temperatures of 200°C and 280°C respectively. The semiconductor surface treatment before ALD and the deposition temperature have a strong impact on the dielectric’s electrical properties, surface morphology, stoichiometry, and impurity concentration. Of several etches considered, cleaning the GaN with a piranha etch produced Al₂O₃/GaN MOS capacitors with the best electrical characteristics. The benefits of growing a native oxide of GaN by dry thermal oxidation before depositing the high-κ dielectric was also investigated; oxidizing at 850°C for 30 minutes resulted in the best dielectric-semiconductor interface quality. Interest in nonpolar (m-plane) GaN (due to its lack of strong polarization field) motivated an investigation into the temperature behavior of Al₂O₃/m-plane GaN MOS capacitors. Nonpolar GaN MOS capacitors exhibited a stable flatband voltage across the measured temperature range and demonstrated temperature-stable operation.

"L’industrie nano repousse constamment les limites de la miniaturisation. Pour les systèmes CMOS à mémoires non-volatiles, des phénomènes qui étaient négligeables autrefois sont à présent incontournables et nécessitent des modèles de plus en plus complexes pour décrire, analyser et prédire le comportement électrique de ces dispositifs.Le but de cette thèse est de répondre aux besoins de l’industriel, afin d’optimiser au mieux les performances des produits avant et après les étapes de production. Cette étude propose des solutions, comme des méthodes de test innovantes pour des technologies telles que les mémoires non-volatiles EEPROM embarquées.La première méthode proposée, consiste à extraire la densité de pièges (NiT) générée, au cours du cyclage, dans l’oxyde tunnel de cellules EEPROM, à partir d’une Macro cellule de test reprenant toutes les caractéristiques d’un produit fini. Les résultats expérimentaux sont ensuite injectés dans un modèle analytique décrivant le phénomène de SILC (Stress Induced Leakage Current) qui est le principal effet issu de ces pièges. La densité de pièges en fonction du nombre de cycles est ensuite extraite par interpolation entre les courbes expérimentales et les courbes simulées par le modèleLa seconde méthode propose une étude de corrélation statistique entre le test traditionnel de mise en rétention et le test de stress électrique aux bornes de l’oxyde tunnel, proposant des temps d’exécution bien plus courts. Cette étude se base sur les populations de cellules défaillantes à l’issue des deux tests. C’est en comparant les distributions sur ces populations qu’une loi de corrélation apparaît sur la tendance comportementale des cellules." / The nano industry constantly extends the size limits, especially for CMOS devices with embedded non-volatile memories. Each size reduction step always induces new challenges caused by phenomenon which were previously negligible. As a result, more complex models are required to describe, analyze and predict as well as possible the electrical behaviors. The main goal of this thesis is to propose solutions to the industry in term of test, to optimize the performances before and after the whole process steps. Thus, this study proposes two innovative methodologies dedicated to embedded non-volatile EEPROM memories based devices.The first of them consists in to extract the post-cycling generated tunnel oxide traps density (NiT), directly from a macro cell. The experimental results are then used to be compared with an analytical model calculation which perfectly describes the Stress Induced Current phenomena (SILC). This electrical current directly comes from the generated traps inside the cells tunnel oxide. An interpolation is then done between the model and the experimental resulting curves, to extract the tunnel oxide traps density.The second study proposes a method of statistical correlation between the traditional retention test and testing of electrical stress across the tunnel oxide which has shorter execution time. This study is based on cell populations after failing both tests. By comparing the distributions of these populations a correlation law appears between the cells behavioral tendencies. Following this study the replacement of long retention tests by shorter electrical stress tests may be considered.