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Advanced integrated circuit (IC) technology has implemented new materials for necessary and timely performance improvements. New materials are now required at both the front-end-of-line (FEoL) and back-end-of-line (BEoL) of the device because simple dimensional scaling with standard materials has come with performance costs that negate dimensional scaling performance improvements. At the FEoL, high-[kappa]/metal gate processes are being developed to reduce gate oxide leakage. At the BEoL, Cu-based metallization and low-[kappa] dielectric materials have been developed to reduce BEoL contribution to RC-propagation delay. Cu-based metallization has required change in integration strategy, which has led to concerns about new material reliability performance. Furthermore, continuing pressure to improve device performance requires that a new, more advanced low-[kappa] dielectric be used, which are mechanically and electrically inferior. These performance demands and greater reliability concerns must be balanced. This kind of balance requires that better understanding of the extrinsic threats to device reliability be understood and is the general area of interest for this work. In particular, this study examines the extent of degradation found in low-[kappa] dielectric when it is exposed to ambient moisture and the potential impact of this degradation on intrinsic reliability performance under electrical stress. The integration method is described for low-[kappa] dielectric processing so that potential damages during process can be explained. Local damages can allow moisture incorporation at the expense of additional dielectric performance and reliability degradation. The molecular form of moisture incorporation into low-[kappa] dielectric and potential process methods to reduce moisture incorporation are also discussed. The electrical reliability performance is shown using interdigitated structures through voltage ramped dielectric breakdown study of inter-metal dielectric (IMD). Clear evidence of dielectric degradation is found after extreme moisture incorporation. Moisture penetration impact is also examined on the long-term reliability of integrated low-[kappa] dielectric using time-dependent dielectric breakdown (TDDB). Results show a dramatic change in the observed field acceleration parameter through moisture exposure that is not easily explained in a standard way according to proposed dielectric breakdown models for low-[kappa] dielectrics. A simple modification of the thermochemical [Epsilon]-model is proposed to explain the results. / text

With the continuous growth of non-linear power electronic components and the increasing penetration of the distributed generation (DG), the potential for degradation in the power quality of the existing grid exists. There are concerns that the total harmonic distortion (THD) could reach unacceptable levels of 5% or higher. Moreover, there is additional potential of the presence of amplified harmonic components in the power network grid when the harmonic frequencies align with the resonant frequencies that are being injected by power electronic components of the DG. The above conditions could increase the electrical stresses on the insulation system of the power system components, and in particular, cable terminations are a concern. Standard cable terminations are designed to operate under power frequency in the power system network and their service life is considered accordingly. The research work aims to provide an understanding of the performance of the stress grading (SG) system of a commercial cable termination when the voltage waveform is distorted due to the presence of harmonics and when the high frequency and high dV/dt voltage waveforms are present from a typical power electronic drive. An aging experiment was performed for over a 600 hour time period using the pulse width modulated (PWM) high-voltage generator to quantify the impact of high frequency stress on SG system of cable termination. Furthermore, the cable termination was tested under power frequency, distorted voltage waveforms composed of fundamental and low order harmonics using an experiment setup that generate distorted voltage waveforms. Diagnostic techniques such as surface potential distribution measurements and surface temperature monitoring are used to analyze the termination performance. The surface tangential field is calculated based on the gradient of the termination surface potential as measured with an electrostatic voltmeter. The study shows that distorted voltage waveforms with high frequency and high dV/dt components, increase the electric field, resistive heating, and surface temperature rise in the terminations that use the field-dependent SG materials. The rise of electric field by as high as 27.1% and surface temperature rise of as high as 17C demonstrates the severity on the cable terminations. Such electric field enhancements for a period of time have a potential to initiate partial discharge that could lead to degradation of the termination. Moreover, surface temperature rise of 17 deg C could reduce the allowable ampacity of the cable conductor, reduce the short circuit levels, and reduce the feeder loading limits. The field-dependent electrical conductivity (σ(E,T)), permittivity (ε), and the temperature dependencies of (σ(E,T) and ε) have strong impact to degrade the electrical and thermal properties of the termination due to stress from the non-sinusoidal distorted voltage waveform. In order to minimize the surface temperature rise from the hotspot and electrical stress enhancement that eventually lead to insulation degradation and failure, the following recommendations are made for a suitable SG design for a termination to handle the severe voltage stress: Apply the capacitively graded termination in the grid where the distortion levels are low. Under the increased total harmonic distortion levels and HF components, resistively grading with higher degree of nonlinearity (achieved through the use of ZnO filler) is beneficial. The utilities could take preventive maintenance on medium voltage power cable accessories to prevent the termination failure before it actually occurs. Researchers could focus to resolve and minimize the rising power quality issues when the distribution generations are operated, improve the power electronic converters, and provide cost-effective harmonic filter solutions for harmonic mitigation.

With the continuous growth of non-linear power electronic components and the increasing penetration of the distributed generation (DG), the potential for degradation in the power quality of the existing grid exists. There are concerns that the total harmonic distortion (THD) could reach unacceptable levels of 5% or higher. Moreover, there is additional potential of the presence of amplified harmonic components in the power network grid when the harmonic frequencies align with the resonant frequencies that are being injected by power electronic components of the DG. The above conditions could increase the electrical stresses on the insulation system of the power system components, and in particular, cable terminations are a concern. Standard cable terminations are designed to operate under power frequency in the power system network and their service life is considered accordingly. The research work aims to provide an understanding of the performance of the stress grading (SG) system of a commercial cable termination when the voltage waveform is distorted due to the presence of harmonics and when the high frequency and high dV/dt voltage waveforms are present from a typical power electronic drive. An aging experiment was performed for over a 600 hour time period using the pulse width modulated (PWM) high-voltage generator to quantify the impact of high frequency stress on SG system of cable termination. Furthermore, the cable termination was tested under power frequency, distorted voltage waveforms composed of fundamental and low order harmonics using an experiment setup that generate distorted voltage waveforms. Diagnostic techniques such as surface potential distribution measurements and surface temperature monitoring are used to analyze the termination performance. The surface tangential field is calculated based on the gradient of the termination surface potential as measured with an electrostatic voltmeter. The study shows that distorted voltage waveforms with high frequency and high dV/dt components, increase the electric field, resistive heating, and surface temperature rise in the terminations that use the field-dependent SG materials. The rise of electric field by as high as 27.1% and surface temperature rise of as high as 17C demonstrates the severity on the cable terminations. Such electric field enhancements for a period of time have a potential to initiate partial discharge that could lead to degradation of the termination. Moreover, surface temperature rise of 17 deg C could reduce the allowable ampacity of the cable conductor, reduce the short circuit levels, and reduce the feeder loading limits. The field-dependent electrical conductivity (σ(E,T)), permittivity (ε), and the temperature dependencies of (σ(E,T) and ε) have strong impact to degrade the electrical and thermal properties of the termination due to stress from the non-sinusoidal distorted voltage waveform. In order to minimize the surface temperature rise from the hotspot and electrical stress enhancement that eventually lead to insulation degradation and failure, the following recommendations are made for a suitable SG design for a termination to handle the severe voltage stress: Apply the capacitively graded termination in the grid where the distortion levels are low. Under the increased total harmonic distortion levels and HF components, resistively grading with higher degree of nonlinearity (achieved through the use of ZnO filler) is beneficial. The utilities could take preventive maintenance on medium voltage power cable accessories to prevent the termination failure before it actually occurs. Researchers could focus to resolve and minimize the rising power quality issues when the distribution generations are operated, improve the power electronic converters, and provide cost-effective harmonic filter solutions for harmonic mitigation.

Dans ce travail, les dégradations des diodes électroluminescentes (DEL) ont été étudiées en identifiant et en évaluant leurs signatures électriques et photométriques en vieillissement accéléré sous stress thermique et électrique. Un prototype de banc de test expérimental a été développé et construit spécifiquement pour cette étude ce qui nous a permis de tester 128 échantillons en appliquant différentes conditions de stress thermiques et électriques. Quatre types différents de DEL ont été étudié avec des caractéristiques techniques similaires (température de couleur, courant nominal, mono-puce,...) mais avec des technologies différentes couvrant les principaux acteurs du marché (Cree, Osram, Philips et Seoul Semiconductor). Les échantillons ont d'abord été caractérisés à leur état initial, puis soumis à des conditions de stress électrique (à 350mA ou 1050mA) et thermique (fixé à 50°C). Les mécanismes de défaillance ont été analysés en étudiant l'évolution des signatures électriques et photométriques. Ces caractérisations ont permis d'évaluer et de déterminer l'origine des dégradations à différents niveaux : puce semi-conductrice, interconnexions, phosphore ou encapsulation du dispositif. Les caractérisations électriques nous ont permis d'identifier les mécanismes de dégradation de la puce semi-conductrice et de déterminer la nature des dégradations au niveau du contact ohmique du dispositif (sous fort courant injecté). Les caractérisations photométriques complètent cette étude en évaluant les dégradations associées à l'optique (encapsulation et packaging). / In this work, the degradation of light emitting diodes (LEDs) is studied by identifying and evaluating their aging signature during the stress time. The custom-made experimental test bench is built for realization of the test measurement. Through this experimental test bench, it allows to test a large amount of LED samples and enable to select different temperature condition and different current stress level. There are four different types of LED with similar characteristic in term of their color temperature, IF, VF, power (1W) and as monochip, but different technology coming from Cree, Osram, Philips and Seoul Semiconductor. The devices are firstly characterized their electrical and photometrical characteristic at their initial state, then they are submitted to different current stress condition at low current stress (350mA) and high current stress (1000mA) while the thermal stress is fixed at one temperature (50°C). The study of these devices failure mechanism is archived by using the primary method based on the electrical and photometrical characterization of the devices that allows to evaluate their degradation at different locations of the device components such as semiconductor chip, interconnection and device's package. The electrical characteristic of the device's I-V curve: at low injected current level and reverse bias allow us to identify the degradation characteristic of device's semiconductor chip, at high injected current level allows us to determine the degradation of device's ohmic contact and photometric characteristic allows us to evaluate the degradation of device's package system.

Le travail de la thèse proposé consiste à étudier, caractériser et modéliser la performance et la fiabilité de composants semi-conducteurs sous conditions extrêmes c’est à dire pendant et après que ces composants ont subi un stress électrique, un stress thermique voire les deux stress en même temps. Les composants semi-conducteurs que nous avons étudiés sont des modules photovoltaïques en silicium monocristallin pour des applications dans les énergies renouvelables. Dans cette étude, ces composants ont été soumis à plusieurs types de dégradations générant des défauts localisés dans la structure des composants. Dans un premier temps, des études approfondies des caractéristiques I(V) et C(V) et des paramètres électriques des modules solaires photovoltaïques ont été réalisées en testant une série de modules sous différentes conditions environnementales afin de fournir des données pertinentes pouvant être utiles pour l'évaluation des performances, la modélisation du fonctionnement et pour la mise en œuvre correcte et complète des modules photovoltaïques. Ces caractérisations ont été complétées par l’étude des défauts créés à l’interface et dans les structures des modules photovoltaïques par les différents stress sur la base de mesures effectuées sur ces mêmes cellules par la technique Deep Level Transient Spectroscopy (DLTS). Grâce à cette technique, nous avons identifié et localisé ces défauts au sein du composant, en déterminant leur énergie d’activation et leur section efficace de capture. Les résultats de notre étude montrent ainsi l’importance des conditions de fonctionnement sur les performances instantanées et sur le long terme des systèmes photovoltaïques. Ils peuvent être exploitables directement dans la conception même des modules silicium voire transposable, en suivant la méthodologie de l’étude que nous proposons à de nouvelles technologies de modules / The objective of this work aim to study the performance, reliability of semiconductor structures after their operation under extreme conditions, during and after electrical stress, thermal stress, and combined electro thermal stresses. The studied semiconductor structures are photovoltaic cells for applications in the field of renewable energies. These devices have been exposed to several types of degradation generating localized defects in the structures. The I (V) and C (V) characteristics and electrical parameters have been studied before and after each stress case. The Deep Level Transient Spectroscopy (DLTS) was used as advanced technique for tracking the defects created at the interface and in the bulk structures. The DLTS technique allows identifying and locating these defects within the devices, by determining their activation energy and their capture cross-Section

This work deals with the influence of multistress ageing (electrical and thermal stress) to relaxation effects depending on defined conditions had being labored.

The diploma thesis with experimental verification influence moisture of the dielectric properties of non-aged and thermally, electric and multistress aged slot insulation Isonom NMN. Above all both components of the complex permittivity are examined in dependence on frequency during the thermal, electric and multistress ageing. Practical part is specialized on design, realization and examination of workplace multistress ageing.

Diploma thesis treat of effect of thermal, electrical and combined (thermal electrical) stress on electrical characteristics of insulation material ISONOM NMN which is used as a slot insulation in electric motors. To monitor the stress is used the method of dielectric relaxation spectroscopy. Under examinations are the resultant dielectric spectra which constitute the frequency dependencies of components of complex permitivity. Compared are the effects of particular stresses on dielectric spectra of surveyed insulative material.

"L’industrie nano repousse constamment les limites de la miniaturisation. Pour les systèmes CMOS à mémoires non-volatiles, des phénomènes qui étaient négligeables autrefois sont à présent incontournables et nécessitent des modèles de plus en plus complexes pour décrire, analyser et prédire le comportement électrique de ces dispositifs.Le but de cette thèse est de répondre aux besoins de l’industriel, afin d’optimiser au mieux les performances des produits avant et après les étapes de production. Cette étude propose des solutions, comme des méthodes de test innovantes pour des technologies telles que les mémoires non-volatiles EEPROM embarquées.La première méthode proposée, consiste à extraire la densité de pièges (NiT) générée, au cours du cyclage, dans l’oxyde tunnel de cellules EEPROM, à partir d’une Macro cellule de test reprenant toutes les caractéristiques d’un produit fini. Les résultats expérimentaux sont ensuite injectés dans un modèle analytique décrivant le phénomène de SILC (Stress Induced Leakage Current) qui est le principal effet issu de ces pièges. La densité de pièges en fonction du nombre de cycles est ensuite extraite par interpolation entre les courbes expérimentales et les courbes simulées par le modèleLa seconde méthode propose une étude de corrélation statistique entre le test traditionnel de mise en rétention et le test de stress électrique aux bornes de l’oxyde tunnel, proposant des temps d’exécution bien plus courts. Cette étude se base sur les populations de cellules défaillantes à l’issue des deux tests. C’est en comparant les distributions sur ces populations qu’une loi de corrélation apparaît sur la tendance comportementale des cellules." / The nano industry constantly extends the size limits, especially for CMOS devices with embedded non-volatile memories. Each size reduction step always induces new challenges caused by phenomenon which were previously negligible. As a result, more complex models are required to describe, analyze and predict as well as possible the electrical behaviors. The main goal of this thesis is to propose solutions to the industry in term of test, to optimize the performances before and after the whole process steps. Thus, this study proposes two innovative methodologies dedicated to embedded non-volatile EEPROM memories based devices.The first of them consists in to extract the post-cycling generated tunnel oxide traps density (NiT), directly from a macro cell. The experimental results are then used to be compared with an analytical model calculation which perfectly describes the Stress Induced Current phenomena (SILC). This electrical current directly comes from the generated traps inside the cells tunnel oxide. An interpolation is then done between the model and the experimental resulting curves, to extract the tunnel oxide traps density.The second study proposes a method of statistical correlation between the traditional retention test and testing of electrical stress across the tunnel oxide which has shorter execution time. This study is based on cell populations after failing both tests. By comparing the distributions of these populations a correlation law appears between the cells behavioral tendencies. Following this study the replacement of long retention tests by shorter electrical stress tests may be considered.