Current requirements of nonvolatile memory (NVM) are the high density cells, low-power consumption, high-speed operation and good reliability for the scaling down devices. However, all of the charges stored in the floating gate will leak into the substrate if the tunnel oxide has a leakage path in the conventional NVM during endurance test. Therefore, the tunnel oxide thickness is difficult to scale down in terms of charge retention and endurance characteristics. The nonvolatile nanocrystal memories are one of promising candidates to substitute for conventional floating gate memory, because the discrete storage nodes as the charge storage media have been effectively improve data retention under endurance test for the scaling down device. Many methods have been developed recently for the formation of nanocrystal. Generally, most methods need thermal treatment with high temperature and long duration. This procedure will influence thermal budget and throughput in current manufacture technology of semiconductor industry. In this thesis, we used the three kind of high-k dielectric structure as the tunnel oxide (Al2O3, HfO2/Al2O3/HfO2, Al2O3/HfO2/Al2O3) to overcome the limitation of conventional NVMs during the scaling down process. First, we used Al2O3 as tunnel oxide. It observed that device of Al2O3 as tunnel oxide reduce equivalent thickness without lost retention too much. Then, we used HfO2/Al2O3/HfO2 as tunnel oxide. It observed the device of HfO2/Al2O3/HfO2 as tunnel oxide which had bigger window than the device used thermal oxide as tunnel oxide. Moreover it had better retention characteristics than the device used thermal oxide as tunnel oxide with a small charge lose rate. And it reduced equivalent thickness of SiO2.Final, we used Al2O3/HfO2/Al2O3 as tunnel oxide. It observed the device of Al2O3/HfO2/Al2O3 as tunnel oxide which had better retention characteristics than the device used HfO2/Al2O3/HfO2 as tunnel oxide without decrease the electron and hole injection. And we reduce equivalent thickness of SiO2 .

De nombreuses applications industrielles spécifiques dans les secteurs tels que l’automobile, le médical et le spatial, requièrent un très haut niveau de fiabilité. Dans ce contexte, cette thèse traite de l’étude de la fiabilité des mémoires non-volatiles à grille flottante de type NOR Flash. Après une introduction mêlant l’état de l’art des mémoires non volatiles et la caractérisation électrique des mémoires Flash, une étude sur l’effet des signaux de polarisation a été menée. Un modèle a été développé afin de modéliser la cinétique de la tension de seuil durant un effacement. L’effet de la rampe d’effacement a été montré sur les cinétiques mais aussi sur l’endurance. Une étude sur la durée de vie de l’oxyde tunnel a ensuite montré l’importance de l’utilisation d’un stress dynamique. Nous avons caractérisé cette dépendance en fonction du rapport cyclique et du champ électrique appliqué. Enfin l’endurance de la cellule mémoire Flash a été étudiée et les effets de la relaxation durant le cyclage ont été analysés. / Many specific applications used in automotive, medical and spatial activity domains, require a high reliability level. In this context, this thesis focuses on the study of floating gate non-volatiles memories reliability more precisely in NOR Flash architecture. After an introduction mixing the state of art of non-volatiles memories and the electrical characterization of Flash memories, a study on the polarization signals effect has been led. A model has been developed in order to model the threshold voltage kinetic during an erase operation. The erasing ramp effect has been shown on kinetics and also on cycling. Then, a study on the tunnel oxide lifetime has shown the importance of relaxation during stress. This dependence has been characterized as a function of duty cycle and the electric field applied. Finally, Flash memory cell endurance has been explored and the relaxation effects during the cycling has been analyzed.

"L’industrie nano repousse constamment les limites de la miniaturisation. Pour les systèmes CMOS à mémoires non-volatiles, des phénomènes qui étaient négligeables autrefois sont à présent incontournables et nécessitent des modèles de plus en plus complexes pour décrire, analyser et prédire le comportement électrique de ces dispositifs.Le but de cette thèse est de répondre aux besoins de l’industriel, afin d’optimiser au mieux les performances des produits avant et après les étapes de production. Cette étude propose des solutions, comme des méthodes de test innovantes pour des technologies telles que les mémoires non-volatiles EEPROM embarquées.La première méthode proposée, consiste à extraire la densité de pièges (NiT) générée, au cours du cyclage, dans l’oxyde tunnel de cellules EEPROM, à partir d’une Macro cellule de test reprenant toutes les caractéristiques d’un produit fini. Les résultats expérimentaux sont ensuite injectés dans un modèle analytique décrivant le phénomène de SILC (Stress Induced Leakage Current) qui est le principal effet issu de ces pièges. La densité de pièges en fonction du nombre de cycles est ensuite extraite par interpolation entre les courbes expérimentales et les courbes simulées par le modèleLa seconde méthode propose une étude de corrélation statistique entre le test traditionnel de mise en rétention et le test de stress électrique aux bornes de l’oxyde tunnel, proposant des temps d’exécution bien plus courts. Cette étude se base sur les populations de cellules défaillantes à l’issue des deux tests. C’est en comparant les distributions sur ces populations qu’une loi de corrélation apparaît sur la tendance comportementale des cellules." / The nano industry constantly extends the size limits, especially for CMOS devices with embedded non-volatile memories. Each size reduction step always induces new challenges caused by phenomenon which were previously negligible. As a result, more complex models are required to describe, analyze and predict as well as possible the electrical behaviors. The main goal of this thesis is to propose solutions to the industry in term of test, to optimize the performances before and after the whole process steps. Thus, this study proposes two innovative methodologies dedicated to embedded non-volatile EEPROM memories based devices.The first of them consists in to extract the post-cycling generated tunnel oxide traps density (NiT), directly from a macro cell. The experimental results are then used to be compared with an analytical model calculation which perfectly describes the Stress Induced Current phenomena (SILC). This electrical current directly comes from the generated traps inside the cells tunnel oxide. An interpolation is then done between the model and the experimental resulting curves, to extract the tunnel oxide traps density.The second study proposes a method of statistical correlation between the traditional retention test and testing of electrical stress across the tunnel oxide which has shorter execution time. This study is based on cell populations after failing both tests. By comparing the distributions of these populations a correlation law appears between the cells behavioral tendencies. Following this study the replacement of long retention tests by shorter electrical stress tests may be considered.