Gallium arsenide MESFETS require protective passivation at several steps in their fabrication. A common film used for device passivation is silicon nitride. This passivation film is deposited on gallium arsenide substrates by chemical vapor deposition techniques and possesses high intrinsic stress. The stresses arise from the difference in the gallium arsenide and silicon nitride material properties, such as coefficient of expansion, density, modulus, and deposition temperature. The stress has been shown to cause electrical performance shifts in GaAs MESFET structures due to the piezoelectric nature of the gallium arsenide lattice. This work develops a framework of mathematical models and experimental techniques by which the intrinsic stresses in the film and the GaAs substrate can be evaluated. Specifically, this work details the stress field and the electrical performance shifts in fully planarized self aligned gate GaAs MESFETS. The devices were 10 micron gate periphery FET devices with a 0.4 micron etched gate length. The test devices included both enhancement mode and depletion mode structures. The major contributors to the stress in GaAs devices was found to be the intrinsic stress effects of the silicon nitride passivation film. An externally applied stress, such as that applied to a package base that a typical GaAs device would be mounted into for actual service, was found to be insufficient to cause significant shifts in the device performance. The package body effectively reduces the transfer of stress to the device body and thereby minimizes the piezoelectric effect. The intrinsic stress effects are due to the deposition of the film itself. This intrinsic stress was found to have a significant effect on the device electrical characteristics. The stress was found to permanently shift the threshold voltage and current in 10 micron self aligned gate MESFETS. The shift was measured at 26 millivolts per 100 MPa film stress for depletion mode devices and 23 millivolts per 100 MPa for enhancement mode devices. For the maximum measured biaxial stress of -0.54 MPa in the gallium arsenide, the total measured shift was 140 millivolts. The level of shift is similar to that reported by earlier researchers. This piezoelectric shift has been modeled, with model predictions within 50/0 of the experimental values for the DFET devices and 11 % for the EFET devices. / Ph. D.

As advances in very large scale integration (VLSI) technology lead to higher levels of circuit integration and new design styles and fabrication processes, traditional test generation techniques fail to adequately address the problems of how to (l) accurately represent the structure of design styles and physical faults, and (2) manage the high computational costs and memory resource requirements caused by the complexity of VLSI. This research investigates a modular, hierarchical approach to test generation for combinational complementary metal oxide semiconductor (CMOS) circuits that effectively deals with these issues. Circuits are modeled using multi-level descriptions to handle large circuit sizes while maintaining an effective balance between accuracy and complexity. Object-oriented analysis and design techniques are used in the development of a hierarchical test generation application implemented using C++. In doing this, the primary objectives were to produce a easily maintainable system, provide an extensible framework for test generation supporting the straightforward incorporation of new types of circuit primitives and faults, and retain the same level of computational efficiency that can be achieved using a procedural language such as C. Characteristics of the object-oriented hierarchical test generation application, such as expandability and run-time efficiency, are compared to those of a standard gate-level test generation program implemented using C and a procedural design approach. / Ph. D.

With a decreasing minimum feature size in very large scale integration (VLSI) complementary metal oxide semiconductor (CMOS) technology, the number of transistors that can be integrated on a single chip is increasing rapidly. Ensuring that these extremely dense chips are almost free of defects, and at the same time, cost-effective requires planning from the initial stage of design. This research proposes a concurrent engineering-based design methodology for layout optimization. The proposed method for layout optimization is iterative, and layout changes in each design iteration are made based on the principles of physical design for testability (P-DFT). P-DFT modifies a design such that the circuit has fewer faults, difficult to detect faults are made easier to detect, and difficult to detect faults are made less likely to occur. To implement this design methodology, a mathematical model is required to evaluate alternate designs. This research proposes an evaluation measure: the cost quality model. The cost quality model extends known test quality and testability estimation measures for gate-level circuits to switch-level circuits. To provide high fidelity in testability estimation and reasonable CPU time overhead, the cost quality model uses inductive fault analysis techniques to extract a realistic circuit fault list, I_DDQ test generation techniques to generate tests for these faults, statistical models to reduce computational overhead due to test generation and fault simulation, yield simulation tools, and mathematical models to estimate test quality and costs. To demonstrate the effectiveness of this model, results are presented for CMOS layouts of benchmark circuits and modifications of these layouts. / Master of Science

The development of the High Frequency Power MOSFET has brought about a need for accurate models. Now that the frequency range of these MOSFETs is in domains where typically scattering parameter measurements are used, a broad band device model can prove to be extremely useful. This thesis summarizes the research performed towards the development of a wideband Gate model for the Motorola MRF162 High Frequency Power Transistor. The device theory for typical MOSFETs will be explained. This theory will lead into the development of the Power MOSFET and its associated frequency limitations. The benefits of Time Domain Techniques will be explained and how a wideband model is achieved from this technique. The result from the analysis of the measurements and the device theory is a wideband Gate model developed for the frequency range from 100MHz to 400MHz. Verification is achieved by curve matching the measured Time Domain Reflected waveforms with the simulated waveforms generated using a proprietary program Modified Transient Analysis Program (MTCAP) and by comparison of expected and simulated parasitic values. / Master of Science

In retrospect we can see that from the last century, wireless electronic technology has been in a rapid state of development. With the popularity of wireless communication, the power amplifier demand is rising. In general, magnitude, maximum noise figure, minimum noise figure, efficiency, and output power are important indicators of the amplifier. The IC industry is exploring how to reduce the additional cost and improve the high-frequency performance. Therefore, designing a strong adaptability and high cost performance of the PA has become a priority. As these technologies advance, the power amplifiers need to have better integration, lower cost, and lower power dissipation. Also, some special requirements are being asked in some areas, such as multi-mode and multi-band. In general, people have to use several power amplifiers parallel to frame a multifunction chip. Each of them working at different frequencies of interest has to have separate matching network, design, and area; also, the diversity amplifier prices will increase with the number of amplifiers, and its cost is also changed. In this thesis, because Class E power amplifier has lower power dissipation, 100% ideal efficiency, simple circuit structure, and strong applicability, the Class E is used as power amplifier in main stage. Moreover, in order to decrease input power and increase output power, the class A power amplifier is used as driver stage. It can use very small amount of power to provide a larger power. Moreover, we use a switched variable inductor and capacitor to constitute a dual band matching network which can let the PA work at more than one frequency. In fact, we design a Class A PA which is as a driver stage. Then, when we support 1 dBm input power, the driver stage can have 8 dBm output power. Also the output will be the input power for the main stage. When the Class E PA get 8dBm input power, it will export a 15dBm output power. Because the dual band matching network, the PA can work at 2.2 GHz and 2.6 GHz; also, the efficiency is 48% and 51%, and the both gains are 13 dB. In the future, in order to further improve the performance of the power amplifier and better multi-frequencies, more new designs with new structures should be investigated. Moreover, we need further research about design theory. In fact multi-frequencies power amplifier has a great potential in real application. It based on its special structure and design parameters.

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This paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage range from the most commonly known mixer design, to implemented design techniques that are used to increase the mixers important design properties as the demand of CMOS technology and the overall RF system rises. All mixer topologies were designed and simulated using TSMC 0.18 µm CMOS technology in Advanced Design Systems, a simulator used specifically for RF designs.