The objective of this research is to demonstrate the feasibility of the implementation of low-cost, small-size, and high power RF front ends using CMOS technology which has been known not to be suitable for high-power applications due to its material characteristic. One part of this research focuses on developing GaAs switches for multi band and multi mode high power applications. The development of RF front end switches for high power applications using CMOS technology is very challenging in that the characteristics of CMOS technology such as low breakdown voltages, slow electron mobility and existence of substrate junction diodes are limiting power handling capability of CMOS technology. Various topologies of CMOS switches have been employed in implementing high power RF front end CMOS switches in order to overcome material limitations of CMOS technology in high power applications. Based on measurement data such as power handling capability and S-parameters of fabricated CMOS switches, the feasibility of use of CMOS technology in high power RF antenna switch design has been studied, and novel methods of designing CMOS switches to improve the power handling capability without compensating S-parameter performance are proposed. As a part of this research, multi-band and multi-mode power switches using GaAs technology are fabricated and tested for use of the commercial applications such as handsets covering GSM, PCS/DCS, and UMTS bands. Current commercial RF switch products demand small size, low cost and low voltage control as the number of wireless standards integrated in a single application increases. This research provides a solution for commercial products which can meet all the specifications as well as needs required in the wireless market.

The objective of the research is to develop analog spectrum processing techniques for cognitive radio (CR) applications in CMOS technology. CR systems aim to use the unoccupied spectrum allocations without any license when the primary users are not present. Therefore, the successful deployment of CR systems relies on their ability to accurately sense the spectrum usage status over a wide frequency range serving various wireless communication standards. Meanwhile, to maximize the utilization of the available spectrum segments, the bandwidth of the signal has to be highly flexible, so that even a small fraction of spectrum resources can be fully utilized by CR users. One of the key enabling technologies of variable bandwidth communication is a tunable baseband filter. In this research, a reconfigurable CR testbed system is presented as groundwork for the researches related with CR systems. With the feasibility study on the multi-resolution spectrum sensing (MRSS) functionality, a method for determining sensing threshold for MRSS functionality is presented, and a fully integrated MRSS receiver in CMOS technology is demonstrated. On the other hand, a reconfigurable CMOS analog baseband filter which can change its bandwidth, type and order with high resolution for CR applications is presented. In sum, an analog spectrum sensing method as well as a highly flexible analog baseband filter architecture is established and implemented in CMOS technology. Both designs are targeting the utilization of the analog signal processing capability with the aid of the digital circuits.

This dissertation presents system and circuit development of the low-power multi-gigabit CMOS demodulator using analog and mixed demodulation techniques. In addition, critical building blocks of the low-power analog quadrature front-ends are designed and implemented using 90 nm CMOS with a targeted compatibility to the traditional demodulator architecture. It exhibits an IF-to-baseband conversion gain of 25 dB with 1.8 GHz of baseband bandwidth and a dynamic range of 23 dB while consuming only 46 mW from a 1 V supply voltage. Several different demodulators using analog signal processor (ASP) are implemented: (1) an ultra-low power non-coherent ASK demodulator is measured to demodulate a maximum speed of 3 Gbps while consuming 32 mW from 1.8 V supply; (2) a mere addition of 7.5 mW to the aforementioned analog quadrature front-end enables a maximum speed of 2.5 Gbps non-coherent ASK demodulation with an improved minimum sensitivity of -38 dBm; (3) a robust coherent BPSK demodulator is shown to achieve a maximum speed of 3.5 Gbps based on the same analog quadrature front-end with only additional 7 mW. Furthermore, an innovative seamless handover mechanism between ASP and PLL is designed and implemented to improve the frequency acquisition time of the coherent BPSK demodulator. These demodulator designs have been proven to be feasible and are integrated in a 60 GHz wireless receiver. The system has been realized in a product prototype and used to stream HD video as well as transfer large multi-media files at multi-gigabit speed.

A frequency synthesizer plays a critical role in defining the performance of wireless systems in terms of measures such as operating frequency range, settling time, phase noise and spur performance, and area/power consumption. As the trend in mobile system design has changed from single-standard systems to multi-standard/multi-application systems, the role of frequency synthesizers has become even more important. As the most popular architecture, a phase-locked loop (PLL)-based frequency synthesizer has been researched over the last several decades; however, many unsolved problems related to the PLL-based synthesizer are still waiting for answers. This dissertation addresses key challenges related to fully integrated PLL-based frequency synthesizers, including the problem of large area consumption of passive components, the inherent reference-spur problem, and the problem of trade-offs between integer-N PLLs and fractional-N PLLs. In this dissertation, new techniques and architectures are presented and developed to address those challenges. First, a low-phase-noise ring oscillator and a capacitor multiplier with a high-multiplication factor efficiently minimize the silicon area of sub-components, and a compact programmable delay-locked loop (DLL)-based frequency multiplier is developed to replace the PLL-based frequency synthesizer. Second, the charge-distribution mechanism for suppressing reference spurs is theoretically analyzed, and an edge interpolation technique for implementing the mechanism is developed. Finally, the concept and the architecture of sub-integer-N PLL is proposed and implemented to remove trade-offs between conventional integer-N PLLs and fractional-N PLLs.

Thesis (M.S.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

The objective of the research in this dissertation is to demonstrate the viability of using silicon-germanium (SiGe) bipolar/complementary metal-oxide semiconductor (BiCMOS) technologies in novel high-speed, high-performance wireless and wireline applications. These applications include self-healing integrated systems, W-Band phased array radar systems, and multi-gigabit wireline transceiver systems. The contributions from this research are summarized below: 1. Design of a wideband 8-18 GHz signal source with the best reported tuning range and die area combination for self-healing applications [95]. 2. Design of a robust, multi-band 8-10/ 16-20 GHz signal source with amplitude-locking for self-healing applications. A figure-of-merit (FoM) is proposed that combines tuning range and die area, and this work achieves the best FoM compared with state-of-the art [51]. 3. First ever reported on-die healing of image-rejection ratio of an 8-18 GHz mixer integrated with the multi-band test signal source [52], [96]. 4. Design of a 94 GHz differential Colpitts oscillator with 14% tuning range that spans 86-99 GHz for phased-array radar systems. 5. Identification of technology platform related bottlenecks in multi-gigabit wireline systems. A novel study of linearity of switching transistors in a current-mode logic (CML) gate. 6. A novel FoM that can be used to predict large-signal CML delay using small-signal Y-parameter techniques [97].

The objective of this research is to design and implement low-noise wideband RFIC components with CMOS technology for the direct-conversion architecture. This research proposes noise reduction techniques to improve the thermal noise and flicker noise contribution of a low noise amplifier (LNA) and a mixer. Of these techniques, the LNA is found to reduce noise, boost gain, and consume a relatively low amount of power without sacrificing the wideband and linearity advantages of a conventional common gate (CG) topology. The research concludes by investigating the proposed mixer topology, which senses and compensates local oscillator (LO) phase mismatches, the dominant cause of flicker noise.

SiGe BiCMOS technology has many advantageous properties that, when leveraged, enable circuit design for extreme environments. This work will focus on designs targeted for space system avioinics platforms under the NASA ETDP program. The program specifications include operation under temperatures ranging from -180 C to +125 C and with radiation tolerance up to total ionizing dose of 100 krad with built-in single-event latch-up tolerance. To the author's knowledge, this work presents the first design and measurement of a wide temperature range enabled, radiation tolerant as built, RS-485 wireline transceiver in SiGe BiCMOS technology. This work also includes design and testing of a charge amplification channel front-end intended to act as the interface between a piezoelectric sensor and an ADC. An additional feature is the design and testing of a 50 Ohm output buffer utilized for testing of components in a lab setting.

Parameter variations, noise susceptibility, and increasing energy dissipation of CMOS devices have been recognized as major challenges in circuit and micro-architecture design in the nanometer regime. Among these, parameter variations and noise susceptibility are increasingly causing CMOS devices to behave in an "unreliable" or "probabilistic" manner. To address these challenges, a shift in design paradigm, from current day deterministic designs to "statistical" or "probabilistic" designs is deemed inevitable. Motivated by these considerations, I introduce and define probabilistic Boolean logic, whose logical operators are by definition "correct" with a probability 1/2 <= p <= 1. While most of the laws of conventional Boolean logic can be naturally extended to be valid in the probabilistic case, there are a few significant departures. We also show that computations realized using implicitly probabilistic Boolean operators are more energy efficient than their counterparts which use explicit sources of randomness, in the context of probabilistic Boolean circuits as well as probabilistic models with state, Rabin automata. To demonstrate the utility of implicitly probabilistic elements, we study a family of probabilistic architectures: the probabilistic system-on-a-chip PSOC, based on CMOS devices rendered probabilistic due to noise, referred to as probabilistic CMOS or PCMOS devices. These architectures yield significant improvements, both in the energy consumed as well as in the performance in the context of probabilistic or randomized applications with broad utility. Finally, we extend the consideration of probability of correctness to arithmetic operations, through probabilistic arithmetic. We show that in the probabilistic context, substantial savings in energy over correct arithmetic operations may be achieved. This is the theoretical basis of the energy savings reported in the video decoding and radar processing applications that has been demonstrated in prior work.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.