With the explosive growth of the wireless market, the demand for low-cost and highly-integrated radio frequency (RF) transceiver has been increased. Keeping up with this trend, complimentary metal-oxide-semiconductor (CMOS) has been spotlighted by virtue of its superior characteristics. However, there are challenges in achieving this goal, especially designing the transmitter portion. The objective of this research is to demonstrate the feasibility of fully integrated CMOS transmitter module which includes power amplifier (PA) and transmit/receive (T/R) switch by compensating for the intrinsic drawbacks of CMOS technology. As an effort to overcome the challenges, the high-power handling T/R switches are introduced as the first part of this dissertation. The proposed differential switch topology and feed-forward capacitor helps reducing the voltage stress over the switch devices, enabling a linear power transmission. With the high-power T/R switches, a new transmitter front-end topology - differential PA and T/R switch topology with the multi-section PA output matching network - is also proposed. The multi-stage PA output matching network assists to relieve the voltage stress over the switch device even more, by providing a low switch operating impedance. By analyzing the power performance and efficiency of entire transmitter module, design methodology for the high-power handling and efficient transmitter module is established. Finally, the research in this dissertation provides low-cost, high-power handling, and efficient CMOS RF transmitter module for wireless applications.

Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL). This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.

Trends toward increased integration and miniaturization of optical system components have created pressure to consolidate widely disparate analog and digital functions onto fewer and fewer chips with a goal of eventually built into a single mixed-signal chip. Yet, because of those performance requirements, the frontend circuit has traditionally used III-V compound semiconductor technologies, but the low-level of integration with other digital ICs limits the sustainability of such end products for short-distance applications. On the other hand, their CMOS counter parts, despite having such advantages as low power consumption, high yield that lowers the cost of fabrication, and a higher degree of integration, have not performed well enough to survive in such a noisy environment without sacrificing other important attributes. In this research, a high-speed CMOS preamplifier was designed and fabricated through TSMC 0.18/spl mu/m mixed-signal non-epi CMOS technology, and a 20/spl mu/m diameter InGaAs thin-film Inverted-MSM photodetector with a responsivity of 0.15A/W at a wavelength of 1550/spl mu/m was post-integrated onto the circuit. The circuit has a overall transimpedance gain of 60dB/spl Omega/, and bit-error-rate data and eye-diagram measurement results taken as high as 10Gbit/s are reported in this dissertation.

Radio Frequency Low Noise and High Q Integrated Filters in Digital CMOS Processes Zhijie Xiong 149 pages Directed by Dr. Phillip E. Allen Presented in this work is a novel design technique for CMOS integration of RF high Q integrated filters using positive feedback and current mode approach. Two circuits are designed in this work: a 100MHz low-noise and high Q bandpass filter suited for an FM radio front-end, and a 2.4GHz low-noise and high-Q bandpass filter suited for a Bluetooth front-end. Current-mode approach and positive feedback design techniques are successfully used in the design of both circuits. Both circuits are fabricated through a 0.18um CMOS process provided by National Semiconductor Corp. The 100MHz circuit achieves 3.15uV RF sensitivity with 26dB SNR, and the total current consumption is 12mA. The center frequency of the filter is tunable from 80MHz to 110MHz, and the Q value is tunable from 0.5 to 28.9. 1 dB compression point is measured as -34.0dBm, combined with noise measurement results, a dynamic range of 54.1 dB results. Silicon area of the core circuit is 0.4 square millimeters. The center frequency of the 2.4GHz circuit is tunable from 2.4GHz to 2.5GHz, and the Q value is tunable from 20 to 120. The 1 dB compression dynamic range of the circuit is 50dB. Integrated spiral inductors are developed for this design. Patterned ground shields are laid out to reduce inductor loss through substrate, especially eddy current loss when the circuit is fabricated on epi wafers. Accumulation mode MOS varactors are designed to tune the frequency response. Silicon area of the core circuit is 1 square millimeter.

The central thesis of this research is that VLSI interconnect design strategies should shift from using global wires that can support only a single binary transition during the latency of the line to global wires that can sustain multiple bits traveling simultaneously along the length of the line. It is shown in this thesis that such throughput-centric multibit transmission can be achieved by wave-pipelining the interconnects using repeaters. A holistic analysis of wave-pipelined interconnect circuits, along with the full-custom optimization of these circuits, is performed in this research. With the help of models and methodologies developed in this thesis, the design rules for repeater insertion are crafted to simultaneously optimize performance, power, and area of VLSI global interconnect networks through a simultaneous application of voltage scaling and wire sizing. A qualitative analysis of latency, throughput, signal integrity, power dissipation, and area is performed that compares the results of design optimizations in this work to those of conventional global interconnect circuits. The objective of this thesis is to study the circuit- and system-level opportunities of voltage scaling, wire sizing, and repeater insertion in wave-pipelined global interconnect networks that are implemented in deep submicron technologies.

Silicon alternatives to quartz crystal based oscillators to electronic system clocking are explored. A study of clocking requirements reveals widely different specifications for different applications. Traditional CMOS oscillator-based solutions are optimized for low-cost fully integrated micro-controller clock applications. The frequency variability of these clock generators is studied and techniques to compensate for this variability are proposed. The efficacy of these techniques in reducing variability is proven theoretically and experimentally. MEMS-resonator based oscillators, due to their exceptional quality factors, are identified as suitable integrated replacements to quartz based oscillators for higher accuracy applications such as data converter clocks. The frequency variation in these oscillators is identified and techniques to minimize the same are proposed and demonstrated. The sources of short-term variation (phase noise) in these oscillators are discussed and an inclusive theory of phase noise is developed. Techniques to improve phase noise are proposed. Findings from this research indicate that MEMS resonator based oscillators, may in future, outperform quartz based solutions in certain applications such as voltage controlled oscillators. The implications of these findings and potential directions for future research are identified.

With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment. Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques. These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic architecture.

This work represents several years' research into the field of radiation hardening by design. The unique characteristics of a SiGe HBT, described in Chapter 1, make it ideally suitable for use in extreme environment applications. Chapter 2 describes the total ionizing dose effects experienced by a SiGe HBT, particularly those experienced on an Earth-orbital or lunar-surface mission. In addition, the effects of total dose are evaluated on passive devices. As opposed to the TID-hardness of SiGe transistors, a clear vulnerability to single-event effects does exist. This field is divided into three chapters. First, the very nature of single-event transients present in SiGe HBTs is explored in Chapter 3 using a heavy-ion microbeam with both bulk and SOI platforms [31]. Then, in Chapter 4, a new device-level SEU-hardening technique is presented along with circuit-design techniques necessarily for its implementation. In Chapter 5, the circuit-level radiation-hardening techniques necessarily to mitigate the effects shown in Chapter 3 are developed and tested [32]. Finally, in Chapter 6, the performance of the SiGe HBT in a cryogenic testing environment is characterized to understand how the widely-varying temperatures of outer space may affect device performance. Ultimately, the built-in performance, TID-tolerance, and now-developing SEU-hardness of the SiGe HBT make a compelling case for extreme environment electronics. The low-cost, high-yield, and maturity of Si manufacturing combine with modern bandgap engineering and modern CMOS to produce a high-quality, high-performance BiCMOS platform suitable for space-borne systems.

This thesis presents circuit-level techniques for soft error mitigation, low-power design with performance trade-off, and variation-tolerant low-power design. The proposed techniques are divided into two broad categories. First, error compensation techniques, which are used for soft error mitigation and also for low-power operation of linear and non-linear filters. Second, a framework for variation tolerant low-power operation of wireless devices is presented. This framework analyzes the effects of circuit "tuning knobs" such as voltage, frequency, wordlength precision, etc. on system performance, and power efficiency. Process variations are considered as well, and the best operating tuning knob levels are determined, which results in maximum system wide power savings while keeping the system performance within acceptable limits. Different methods are presented for variation-tolerant and power-efficient wireless communication. Techniques are also proposed for application driven low-power operation of the OFDM baseband receiver.

This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.