In recent years, tremendous growth of the wireless market can be defined through the following words: smartphone and high-data rate wireless communication. This situation gives new challenges to RF power amplifier design, which includes high-efficiency, multi-band operation, and robustness to antenna mismatch conditions. In addition to these issues, the industry and consumers demand a low-cost small-sized wireless device. A fully integrated single-chip CMOS transceiver is the best solution in terms of cost and level of integration with other functional blocks. Therefore, the effective approaches in a CMOS process for the abovementioned hurdles are highly desirable. In this dissertation, the new challenges are overcome by introducing adaptability to a CMOS power amplifier. Meaningful achievements are summarized as follows. First, a new CMOS switched capacitor structure for high power applications is proposed. Second, a dual-mode CMOS PA with an integrated tunable matching network is proposed to extend battery lifetime. Third, a switchless dual-band matching structure is proposed, and the effectiveness of dual-band matching is demonstrated with a fully-integrated CMOS PA. Lastly, a reconfigurable CMOS PA with an automatic antenna mismatch recovery system is presented, which can maintain its original designed performance even under various antenna mismatch conditions. Conclusively, the research in this dissertation provides various solutions for new challenges of advanced mobile terminals.

The objective of this research is to develop novel capacitive micromachined ultrasonic transducer (CMUT) arrays for intravascular ultrasonic (IVUS) imaging along with the fabrication processes to allow for monolithic integration of CMUTs with custom CMOS electronics for improved performance. The IVUS imaging arrays include dual-ring arrays for forward-looking volumetric imaging in coronary arteries and annular-ring arrays with dynamic focusing capabilities for side-looking cross sectional imaging applications. Both are capable of integration into an IVUS catheter 1-2 mm in diameter. The research aim of monolithic integration of CMUTs with custom CMOS electronics has been realized mainly through the use of sloped sidewall vias less than 5 µm in diameter, with only one additional masking layer as compared to regular CMUT fabrication. Fabrication of CMUTs has been accomplished with a copper sacrificial layer reducing isolation layers by 50%. Modeling techniques for computational efficient analysis of CMUT arrays were developed for arbitrary geometries and further expanded for use with larger signal analysis. Dual-ring CMUT arrays for forward-looking volumetric imaging have been fabricated with diameters of less than 2 mm with center frequencies at 10 MHz and 20 MHz, respectively, for an imaging range from 1 mm to 1 cm. These arrays, successfully integrated with custom CMOS electronics, have generated 3D volumetric images with only 13 cables necessary. Performance from optimized fabrication has reduced the bias required for a dual-ring array element from 80 V to 42 V and in conjunction with a full electrode transmit array, it was shown that the SNR can be improved by 14 dB. Simulations were shown to be in agreement with experimental characterization indicated transmit surface pressure in excess of 8 MPa. For side-looking IVUS, three versions of annular CMUT arrays with dynamic focusing capabilities have been fabricated for imaging 1 mm to 6 mm in tissue. These arrays are 840 µm in diameter membranes linked to form 8 ring elements with areas that deviate by less than 25 %. Through modeling and simulation undesirable acoustic cross between ring elements was reduced from -13 dB to -22 dB.

The objective of this research is to develop an understanding of the trade-offs between performance and reliability in sub 100-nm silicon-on-insulator (SOI) CMOS technologies. Such trade-offs can be used to demonstrate high performance reliable circuits in scaled technologies. Several CMOS reliability concerns such as hot-carrier stress, ionizing irradiation damage, RF stress, temperature effects, and single-event effects are studied. These reliability mechanisms can cause temporary or permanent damage to the semiconductor device and to the circuits using them. Several improvements are made to the device layout and process to achieve optimum performance. Parasitics are shown to play a dominant role in the performance and reliability of sub 100-nm devices. Various techniques are suggested to reduce these parasitics, such as the use of the following: a) optimum device-width, b) optimum gate-finger to gate-finger spacing, c) optimum source/drain metal contact spacing, and d) floating-body/body-contact. The major contributions from this research are summarized as follows: 1) Role of floating-body effects on the performance and reliability of sub 100-nm CMOS-on-SOI technologies is investigated for the first time [1], [2]. It is demonstrated through experimental data and TCAD simulations that floating-body devices have improved RF performance but degraded reliability compared to body-contacted devices. 2) Floating-body effects in a cascode core is studied. Cascode cores are demonstrated to achieve much larger reliability lifetimes than a single device. A variety of cascode topologies are studied to achieve the trade-o s between performance and reliability for high-power applications [2]. 3) The use of body-contact to modulate the performance of devices and single-poledouble- throw (SPDT) switches is studied. The SPDT switch performance is shown to improve with a negative body-bias. 4) The impact of device width on the RF performance and reliability is studied. Larger width devices are shown to have greater degradation, posing challenging questions for RF design in strained-Si technologies [3]. 5) A novel study showing the e ect of source/drain metal contact spacing and gate-finger to gate-finger spacing on the device RF performance is carried out. Further, the impact of above on the hot-carrier, RF stress, and total-dose irradiation tolerance is studied [3], [4]. 6) Latchup phenomenon in CMOS is shown to be possible at cryogenic temperatures (below 50 K), and its consequences are discussed [5]. 7) A time-dependent device degradation model has been developed in technology computer aided design (TCAD) to model reliability in CMOS and SiGe devices. 8) The total-dose irradiation tolerance and hot-carrier reliability of 32-nm CMOSon- SOI technology is reported for the first time. The impact of HfO2 based gate dielectric on the performance and reliability is studied [6]. 9) The impact of technology scaling from 65-nm to 32-nm on the performance and reliability of CMOS technologies is studied [6]. 10) Cryogenic performance and reliability of 45-nm nFETs is investigated. The RF performance improves significantly at 77 K. The hot-carrier device reliability is shown to improve at low temperatures in short-channel CMOS technologies.

Graphene, a single sheet of carbon atoms sp2-bonded in a honeycomb lattice, is a possible all-carbon successor to silicon electronics. Ballistic conduction at room temperature and a linear dispersion relation that causes carriers to behave as massless Dirac fermions are features that make graphene promising for high-speed, low-power devices. The critical advantage of epitaxial graphene (EG) grown on SiC is its compatibility with standard lithographic procedures. Surface X-ray diffraction (SXRD) and scanning tunneling microscopy (STM) results are presented on the domain structure, interface composition and stacking character of graphene grown on both polar faces of semi-insulating 4H-SiC. The data reveal intriguing differences between graphene grown on these two faces. Substrate roughening is more pronounced and graphene domain sizes are significantly smaller on the SiC (0001) Si-face. Specular X-ray reflectivity measurements show that both faces have a carbon rich, extended interface that is tightly bound to the first graphene layer, leading to a buffering effect that shields the first graphene layer from the bulk SiC, as predicted by ab initio calculations. In-plane X-ray crystal truncation rod analysis indicates that rotated graphene layers are interleaved in C-face graphene films and corresponding superstructures are observed in STM topographs. These rotational stacking faults in multilayer C-face graphene preserve the linear dispersion found in single layer graphene, making EG electronics possible even for a multilayer material.

Silicon-germanium (SiGe) BiCMOS technology platforms have proven invaluable for implementing a wide variety of digital, RF, and mixed-signal applications in extreme environments such as space, where maintaining high levels of performance in the presence of low temperatures and background radiation is paramount. This work will focus on the investigation of the total-dose radiation tolerance of a third generation complementary SiGe:C BiCMOS technology platform. Tolerance will be quantified under proton and X-ray radiation sources for both the npn and pnp HBT, as well as for an operational amplifier built with these devices. Furthermore, a technique known as junction isolation radiation hardening will be proposed and tested with the goal of improving the SEE sensitivity of the npn in this platform by reducing the charge collected by the subcollector in the event of a direct ion strike. To the author's knowledge, this work presents the first design and measurement results for this form of RHBD.

Extreme environment applications impose stringent demands on technology platforms that are incorporated in electronic systems. Space is a classic extreme environment, encompassing both large temperature fluctuations as well as intense radiation fields. Silicon-germanium technology has emerged as a competitive platform for space-based applications, owing to its excellent low-temperature performance and total ionizing dose tolerance. This technology has however been repeatedly shown to be vulnerable to single event phenomena induced by galactic cosmic rays as well as trapped particles within the earth's geomagnetic field. To improve the radiation tolerance of systems incorporating SiGe components, modifications to fabrications steps (Radiation Hardening by Process, RHBP) and/or device/circuit topologies (Radiation Hardening by Design, RHBD) may be employed. For this thesis, two methodologies are analyzed, both RHBD techniques which come at no additional power/area penalty for implementation.

Thesis (Ph. D.)--Ohio State University, 2007. / Full text release at OhioLINK's ETD Center delayed at author's request

Thesis (M.Eng.(Microelectronic Engineering))--University of Pretoria, 2009. / Includes summaries in Afrikaans and English. Includes bibliographical references (leaves [74]-78). Mode of access: World Wide Web.

Thesis (M. App. Sc.)--Carleton University, 2005. / Includes bibliographical references (p. 79-82). Also available in electronic format on the Internet.

Thesis (M.App.Sc.) - Carleton University, 2006. / Includes bibliographical references (p. 80-82). Also available in electronic format on the Internet.