Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 73-76). Also available in electronic format on the Internet.

Orientador: Carlos Alberto dos Reis Filho / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-14T00:43:32Z (GMT). No. of bitstreams: 1 Coimbra_RicardoPureza_M.pdf: 4991793 bytes, checksum: 2b5fb9293ae9abe4c248964485ff74e3 (MD5) Previous issue date: 2009 / Resumo: Fontes de referência de tensão e sensores de temperatura são blocos extensivamente utilizados em sistemas microeletrônicos. Como alternativa à aplicação de estruturas consolidadas, mas protegidas por acordos de propriedade intelectual, é permanente a demanda pelo desenvolvimento de novas técnicas e estruturas originais destes circuitos. Também se destaca o crescente interesse por soluções de baixa tensão, baixo consumo e compatíveis com processos convencionais de fabricação. Este trabalho descreve o desenvolvimento de um circuito que atende a estas exigências, fornecendo uma tensão de referência e um sinal de sensoriamento térmico, obtidos a partir de um arranjo adequado de transistores MOS, que operam em regime de forte inversão. O princípio de operação do circuito desenvolvido foi inspirado no conceito de que é possível empilhar n transistores MOS, polarizados com corrente adequada, de tal forma que a queda de tensão sobre a pilha de transistores, com amplitude nVGS, apresente a mesma taxa de variação térmica que a tensão VGS produzida por um único transistor. Nesta condição, a diferença entre as duas tensões é constante em temperatura, constituindo-se em uma referência de tensão. No entanto, o empilhamento de dois ou mais transistores impossibilita a operação do circuito sob baixa tensão. Isto motivou a adaptação da técnica, obtendo a tensão nVGS com o auxílio de um arranjo de resistores, sem o empilhamento de transistores. Desta forma, o potencial limitante da tensão mínima de alimentação tornou-se a própria tensão de referência, cuja amplitude é próxima de um único VGS. A estrutura desenvolvida fornece também um sinal de tensão com dependência aproximadamente linear com a temperatura absoluta, que pode ser aplicado para sensoriamento térmico. Foram fabricados protótipos correspondentes a diversas versões de dimensionamento do circuito para comprovação experimental de seu princípio de operação. O melhor desempenho verificado corresponde à geração de uma tensão de referência com coeficiente térmico de 8,7ppm/ºC, no intervalo de -40ºC a 120ºC, operando com tensão de 1V. Embora o estado da arte seja representado por índices tão baixos quanto 1ppm/ºC, para a mesma faixa de temperatura, a característica compacta do circuito e seu potencial de aplicação sob as condições de baixa tensão e baixo consumo lhe conferem valor como contribuição para este campo de pesquisa e desenvolvimento. / Abstract: Voltage references and temperature sensors are blocks extensively used in microelectronic systems. As an alternative to the use of consolidated structures that are protected by intellectual property agreements, there is a permanent demand for the development of new techniques and structures for these circuits. It can be also highlighted the growing interest for low-voltage and low-power solutions, implemented in conventional IC technologies. This work describes the development of a circuit that meets these requirements by providing a voltage reference and temperature sensing signal obtained from a suitable arrangement of MOS transistors biased in strong inversion. The operation principle of the circuit developed is based on the concept that it is possible for a stack of n MOS transistors, biased by an appropriate current, to show a voltage drop, equal to nVGS, with the same thermal variation rate as a VGS voltage produced by a single transistor. Hence, the difference between the two voltage signals is temperature independent, characterizing a voltage reference. However, the stacking of two or more transistors prevents the operation of the circuit under low voltage. This fact motivated to adapt the technique by obtaining the voltage nVGS with the aid of an array of resistors and no stacked transistors. The minimum supply voltage becomes limited only by the reference voltage itself, whose amplitude is close to a single VGS. The circuit developed also provides a voltage signal almost linearly dependent with the absolute temperature, which can be applied for thermal sensing. Prototypes corresponding to various dimensional versions of the circuit were produced to experimentally verify the principle of operation. The best performance corresponds to the generation of a voltage reference signal with 8.7ppm/ºC thermal coefficient, from -40ºC to 120ºC, under a 1V supply voltage. Although the state of the art is represented by values as low as 1ppm/ºC, at the same temperature range, the circuit's compact aspect together with the possibility to attend low-voltage and low-power requirements grants it value as contribution to this field of research and development / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

Orientador: José Alexandre Diniz / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-21T10:50:41Z (GMT). No. of bitstreams: 1 Silva_AudreyRoberto_M.pdf: 3023922 bytes, checksum: ee750f675d01f2b3ceebd5d74149b16e (MD5) Previous issue date: 2012 / Resumo: Este trabalho apresenta o desenvolvimento de células fotovoltaicas de junção n+/p em substratos de Si com processos de fabricação totalmente compatíveis com a tecnologia CMOS (Complementary Metal Oxide Semiconductor). Os processos compatíveis desenvolvidos neste trabalho sao as técnicas: i) de texturização da superfície do Si, com reflexao da superficie texturizada de 15% obtida com a formação de micro-pirâmides (alturas entre 3 e 7 ?m), utilizando-se solução alcalina de NH4OH (hidróxido de amônia), que e livre da contaminação indesejável por íons de Na+ e K+ quando se utiliza soluções tradicionais de NaOH e de KOH, respectivamente, e ii) de deposição ECR-CVD (Electron Cyclotron Resonance - Chemical Vapor Deposition) da camada antirrefletora (ARC) de SiNX (nitreto de silício), que e executada em temperatura ambiente, portanto pode ser feita apos a finalização da célula sem danificar trilhas metálicas e alterar a profundidade da junção n+/p. A caracterização desta camada ARC mostrou que o nitreto tem índice de refração de 1,92 e refletância mínima de 1,03%, o que e um excelente resultado para uso em células solares (ou fotovoltaicas). Foram fabricadas cinco series de células fotovoltaicas, utilizando-se a texturização com NH4OH e a camada antirrefletora de nitreto de Si. Em quatro series utilizou-se o processo de implantação de íons de fósforo (31P+), com posterior recozimento, para a formação da região n+, enquanto que na quinta serie foi utilizado o processo de difusão térmica. As eficiências máximas para as células fabricadas são de 9% e de 12%, respectivamente, para as células feitas utilizando os processos de implantação e de difusão térmica, indicando que a implantação de íons causa danos na rede cristalina do silício, que o posterior recozimento não consegue corrigir, o que reduz a eficiência da célula / Abstract: This work presents the development of photovoltaic cells based on n+/p junction in Si substrates, with fully compatible fabrication processes with CMOS technology. The compatible processes, which are developed in this study, are the techniques: i) of Si surface texturing, with the textured surface reflection of 15% obtained by the formation of micro-pyramids (heights between 3 and 7 ?m) using NH4OH (ammonium hydroxide) alkaline solution, which is free of undesirable contamination by Na + and K + ions, when NaOH and KOH traditional solutions are used, respectively, and ii) of the ECR-CVD (Electron Cyclotron Resonance - Chemical Vapor Deposition) deposition of SiNx (silicon nitride) anti-reflective coating (ARC), which is carried out at room temperature and can be performed after the end of cell fabrication without damage on metallic tracks and without variation of n+/p junction depth. The ARC coating characterization presented that the silicon nitride has a refractive index of 1.92 and a minimum reflectance of 1.03%, which is an excellent result for application in solar (or photovoltaic) cells. Five series of photovoltaic cells were fabricated, using the NH4OH solution texturing and the silicon nitride antireflective coating. In the first four series, phosphorus (31P+) ion implantation process, with subsequent annealing to get the region n+, was used, while, in the fifth series was used the thermal diffusion process. The maximum efficiency values are of 9% and 12%, respectively, for cells, which were fabricated using the ion implantation and thermal diffusion processes, indicating that the ion implantation damages the silicon crystal lattice and the subsequent annealing cannot rectify, which reduces the cell efficiency / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

The development of new materials and processes for electronic devices has been driven by the integrated circuit (IC) industry since the dawn of the computer era. After several decades of '"Moore's Law"-type innovation, future miniaturization may be slowed down by materials and processing limitations. By way of comparison, the nascent field of flexible electronics is not driven by the smallest possible circuit dimension, but instead by cost and form-factor where features typical of 1970s CMOS (i.e., channel length - IO μm) will enable flexible electronic technologies such as RFID, e-paper, photovoltaics and health monitoring devices. In this thesis. cyclohexasilane is proposed and used as a key reagent in solution processing of poly-Si and Co-Si thin films with the former used as the active layer in thin film transistors (TFTs) and the latter as the gate metal in metal-oxide-semiconductor (MOS) capacitors. A work function of 4.356 eV was determined for the Co-Si thin films via capacitance-voltage (C-Y) characterization which differs slightly from that extracted from ultraviolet photoemission spectroscopy (UPS) data (i.e., 4.8 eV). Simulation showed the difference between the C-V and UPS-derived data may be attributed to the existence of 8.3 x 10 (exponent 10) cm-2 interface charge density in the oxide-semiconductor junction. Poly-Si TFTs prepared using Si6 H12-based inks maintained the following electrical attributes: field effect mobility of 0.1 cm2V-1s-1; threshold voltage of 66 V; and, an on/off ratio of 1630. A BSIM3 version 3 NFET model was modified through global parametric extraction procedure to match the transfer characteristics of the fabricated poly-Si TFT. It is anticipated that this model can be utilized for future design simulation for solution-processed poly-Si circuits.

This is my thesis research on the preparation of borylazadipyrromethene (azaBODIPY) dyes bearing an anchoring group, such as a carboxylic acid group, at the β-pyrrolic position of the azadipyrromethene scaffold. Carboxylate groups form covalent bonds to oxide semiconductors such as TiO2 (n-type) or Cu2O (p-type) in dye-sensitized solar cells (DSCs) or photogalvanic dye-sensitized solar cells (P-DSCs). Oxide-binding azaBODIPY dyes can be used to investigate the rate and mechanism of electron injection from the dyes to the semiconductors. Two different types of azaBODIPY (difluoroboryl and dialkynylboryl) were prepared by following previously developed methods. To convert difluoroborylazaBODIPY to the final dyes having a carboxylic acid in the β-pyrrolic position, several distinct synthetic routes were designed, adopting various reactions, such as halogenation, Sonogashira coupling, Knoevenagel condensation, Grignard reagents, Vilsmeir-Haack, and Steglich esterification. Some of these reactions were successful, but the overall synthesis to the targeted final molecule couldn’t be accomplished. Even though further studies on the synthesis of oxide-binding azaBODIPYs are needed, at least my thesis research suggests what reactions can be implemented to complete this synthesis in the future. Proton NMR (nuclear magnetic resonance) and carbon NMR were commonly used to confirm the synthesized compounds, and sometimes crystallographic information was obtained by XRD (X-ray diffraction) whenever crystals of sufficient size and quality were grown. NMR spectra, interpreted by SpinWorks 3 software, and crystal structures will be introduced in each chapter.

Heterojunctions were generated between tungsten trioxide and tetraphenyl porphyrin with reduced graphene oxide or exfoliated graphite support for mineralisation of acid blue 25 dye under visible light radiation. Moreover, degradation of pharmaceuticals was conducted using p-n heterojunctions between WO3 and Co3O4 and a direct Z-scheme heterojunction between BiOI and Co3O4 prepared using in-situ method and solvothermal self-assembly method respectively. The synthesized materials were characterised using Raman, FTIR, SEM/EDS, TEM, XRD, TGA, BET, UV-Vis and PL techniques. UV-Vis, TOC and HPLC-QTOF-MS were used to study the degradation efficiency and pathway. Scavenger trapping experiments were conducted to propose the charge transfer mechanisms. The highest degradation efficiency (99 %) was achieved for the dye and the pharmaceuticals using visible light. The mineralisation ability of the fabricated nanomaterials was pH dependent with acidic conditions favouring the removal of the dye (pH 5) while alkaline conditions favoured the mineralisation of pharmaceuticals (pH 10 – 11). / Civil and Chemical Engineering

The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (VT) shift and 25% to electron mobility (μn) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and iii device aging such as threshold voltage shift and electron mobility degradation. Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.

A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.

Silicon based 3D fin structure is believed to be the potential future of current semiconductor technology. However, there are significant challenges still exist in realizing a manufacturable fin based process. In this work, we have studied the effects of hydrogen anneal on the structural and electrical characteristics of silicon fin based devices: tri-gate, finFET to name a few. H₂ anneal is shown to play a major role in structural integrity and manufacturability of 3D fin structure which is the most critical feature for these types of devices. Both the temperature and the pressure of H₂ anneal can result in significant alteration of fin height and shape as well as electrical characteristics. Optimum H₂ anneal is required in order to improve carrier mobility and device reliability as shown in this work. A new hard-mask based process was developed to retain H₂ anneal related benefit while eliminating detrimental effects such as reduction of device drive current due to fin height reduction. We have also demonstrated a novel 1T-1C pseudo Static Random Access Memory (1T-1C pseudo SRAM) memory cell using low cost conventional tri-gate process by utilizing selective H₂ anneal and other clever process techniques. TCAD-based simulation was also provided to show its competitive advantage over other types of static and dynamic memories in 45nm and beyond technologies. A high gain bipolar based on silicon fin process flow was proposed for the first time that can be used in BiCMOS technology suitable for low cost mixed signal and RF products. TCAD-based simulation results proved the concept with gain as high 100 for a NPN device using single additional mask. Overall, this work has shown that several novel process techniques and selective use of optimum H₂ anneal can lead to various high performance and low cost devices and memory cells those are much better than the devices using current conventional 3D fin based process techniques. / text

This thesis evaluates the suitability of silicon-germanium technology for electronic systems intended for extreme environments, such as ambient temperatures outside of military specification (-55 degC to 125 degC) range and intense exposures to ionizing radiation. Silicon-germanium devices and circuits were characterized at cryogenic and high-temperatures (up to 300 degC) and exposed to ionizing radiation, providing empirical evidence that silicon-germanium is an excellent platform for terrestrial and space-based electronic applications.