Thesis (M.App.Sc.) - Carleton University, 2002. / Includes bibliographical references (p. 93-95). Also available in electronic format on the Internet.

Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 110-113). Also available in electronic format on the Internet.

Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 112-118). Also available in electronic format on the Internet.

Thesis (M.App.Sc.) - Carleton University, 2006. / Includes bibliographical references (p. 124-128). Also available in electronic format on the Internet.

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 143-145). Also available in electronic format on the Internet.

Orientador: Jacobus Willibrordus Swart / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-12T18:12:37Z (GMT). No. of bitstreams: 1 Campos_FernandodeSouza_D.pdf: 2206636 bytes, checksum: f20b690f268876e5aef018b4b97266ac (MD5) Previous issue date: 2008 / Resumo: O trabalho apresentado nesta tese endereça dois importantes desafios impostos pela evolução da tecnologia CMOS, a diminuição da responsividade das junções e a redução da tensão de alimentação. Um fotodetector de alta responsividade e um sistema de imagem CMOS multiamostrado no domínio do tempo são propostos nesta tese. Como fototransistor de elevada responsividade propõem-se nesta tese o uso do Transistor Bipolar Lateral Controlado por Porta (GC-LBJT) operando como fototransistor de 4 terminais. Apresenta-se a análise do princípio de funcionamento e o desenvolvimento de um circuito equivalente CC. A fotoresposta do GC-LBJT é investigada em duas diferentes configurações, coletor-comum com tensão porta-base constante e emissor-comum com tensão porta-emissor constante. A característica da fotoresposta é associada às equações do dispositivo em ambas as configurações mostrando os principais parâmetros do dispositivo que determinam o ganho. Na configuração coletor-comum, a característica da fotoresposta varia de aproximadamente linear a sublinear por meio da tensão de controle VGB. Na configuração emissor-comum, o dispositivo apresenta fotoresposta sublinear e baixa excursão para toda faixa de tensão de controle (VGB) utilizada. Explorando a característica controlável do GC-LBJT em ambas as configurações, o fototransistor GC-LBJT pode apresentar ganho e responsividade maiores do que 10+6 e 10+4 A/W respectivamente. Propõe-se o método de múltipla-amostragem para sistemas de imagem CMOS no domínio do tempo. O pixel é composto por um comparador e um circuito de memória de um bit. O método de múltipla-amostragem no domínio do tempo permite reduzir o circuito de memória integrado ao pixel de 8 bits tipicamente para um único bit. O resultado da amostra armazenado na memória de um bit no pixel é lida externamente de forma síncrona e o valor do sinal do pixel é codificado de acordo com o instante da amostra no tempo. O número de bits e a velocidade de operação do circuito limitam a dimensão máxima da matriz. Além disso, este trabalho apresenta a influência da não-linearidade da capacitância do fotodiodo na característica da fotoresposta dos sistemas de imagem CMOS no domínio do tempo. Estudo do comportamento do ruído de padrão fixo e o temporal em sistema de imagem no domínio do tempo também são apresentados / Abstract: This thesis adresses two important challenges imposed by CMOS technology trends, the reduction of the junctions's responsivity and voltages levels. A new photodetector with high responsivity and a multi-sampling time domain image system are investigated. This thesis proposes to use the gate controlled lateral bipolar junction transistor (GCLBJT) as a four terminal phototransistor as photodetector with high responsivity. This work presents the photopolarization principle, gain current mechanism of the GC-LBJT in conjuction with DC equivalent circuit development. The GC-LBJT photo response is analysed in two different configurations, common colector with constant gate-base voltage and common emmiter with constant gate-emitter voltage. The photoresponse is related to device equations in both configurations. In the common colector with constant gate-base voltage configuration the photo response characteristic changes from linear to sublinear according to the VGB control voltage. In the common emmiter configuration, the device presents sublinear photo response and small changes for full range of the VGB control voltage used. Exploring the GC-LBJT controllable characteristic, the GC-LBJT phototransistor presents high and controllable gain all over the range of irradiation used, for both configurations. The multi-sampling method for time domain CMOS image systems is proposed. The pixel's architecture is composed by a comparator and a single bit memory circuit. The multisampling method in time-domain allows reducing memory circuits integrated per pixel with eight bit tipically to a single bit. The sample result stored in the single bit memory of the pixel is externally read in a synchronous way and the pixel signal value is coded according to the sampling instant. The number of the bits and the speed of circuit's operation define the upper limit of the matrix size. In addition, this work presents the influence of non-linearity on photoresponse characteristic for systems operating in time domain. The behavior of fixed and temporal pattern noise study in time domain image system is also presented / Doutorado / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

Orientadores: Jacobus Willibrordus Swart, Jader Alves de Lima Filho / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-08T17:33:52Z (GMT). No. of bitstreams: 1 Agostinho_PetersonRibeiro_M.pdf: 4830694 bytes, checksum: d3db6a2118db3df2774037e49df52865 (MD5) Previous issue date: 2006 / Resumo: Este trabalho descreve o procedimento de projeto de amplificadores operacionais rail-to-rail em tecnologia CMOS. Para isto, foram objetos desse processo quatro configurações distintas. As quatro topologias utilizam estágio de entrada rail-to-rail com controle de gm e estágio de saída classe-AB com controle de corrente quiescente. Como especificação para as três primeiras configurações estão tensão de alimentação de ± 0.9V, ganho de manha aberta em baixas freqüências de 60dB e freqüência de ganho unitário de 4MHz para uma carga externa de 10k? em paralelo com 10pF. A quarta configuração é uma nova topologia adaptada para que os transistores operem na região de inversão fraca, com o objetivo de reduzir o consumo de potência. Como especificação para esta configuração temos tensão de alimentação de ± 0.75V e minimização do consumo de potência. Os resultados obtidos a partir dos protótipos fabricados em tecnologia CMOS 0.35µm foram próximos às especificações. Uma placa de circuito impresso foi implementada para caracterização dos amplificadores e, além disso, foi utilizado nessa placa um amplificador comercial para realizar comparações / Abstract: This dissertation describes the process of designing rail-to-rail operational amplifiers in CMOS technology. To accomplish this, the author focused on four distinct structures. The four topologies have rail-to-rail input stage with gm-control circuit and Class-AB output stage with quiescent-current control. The specification of three configurations included the nominal power supply of ± 0.9V, minimum open-loop low-frequency gain of 60dB and unity-gain frequency of 4MHz driving an external load of 10k? in parallel with 10pF. The fourth one is a new topology adapted to operate with transistors in weak inversion, in order to decrease the power consumption. The specification included nominal power supply of ± 0.75V and minimization of power consumption. Prototypes of the amplifiers were fabricated in 0.35µm CMOS technology and the results were in good agreements with the specifications. A printed circuit board was implemented to test the amplifiers and, additionally, was inserted a commercial amplifier, to make comparisons / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

In recent years, advanced high κ gate dielectrics are under serious consideration to replace SiO2 and SiON in semiconductor industry. Hafnium-based dielectrics such as hafnium oxides, oxynitrides and Hf-based silicates/nitrided silicates are emerging as some of the most promising alternatives to SiO2/SiON gate dielectrics in complementary metal oxide semiconductor (CMOS) devices. Extensive efforts have been taken to understand the effects of hydrogen impurities in semiconductors and its behavior such as incorporation, diffusion, trapping and release with the aim of controlling and using it to optimize the performance of electronic device structures. In this dissertation, a systematic study of hydrogen trapping and the role of carbon impurities in various alternate gate dielectric candidates, HfO2/Si, HfxSi1-xO2/Si, HfON/Si and HfON(C)/Si is presented. It has been shown that processing of high κ dielectrics may lead to some crystallization issues. Rutherford backscattering spectroscopy (RBS) for measuring oxygen deficiencies, elastic recoil detection analysis (ERDA) for quantifying hydrogen and nuclear reaction analysis (NRA) for quantifying carbon, X-ray diffraction (XRD) for measuring degree of crystallinity and X-ray photoelectron spectroscopy (XPS) were used to characterize these thin dielectric materials. ERDA data are used to characterize the evolution of hydrogen during annealing in hydrogen ambient in combination with preprocessing in oxygen and nitrogen.

This dissertation has two intersecting foci; firstly, the discovery of a new methodology for the growth of high surface area cuprous oxide (Cu2O) substrates. Secondly, the synthesis and characterization of electron-accepting molecules, and their incorporation into excitonic solar cells (XSCs) using the Cu2O substrates as electrodes. Increasing the surface area of the semiconductor creates more locations for charge transfer to occur thus increasing the overall efficiency of the device. Zinc oxide (ZnO) has been widely studied, and can be easily grown into many different films with high surface area morphologies. The ZnO films serve as sacrificial templates that allow us to electrochemically grow new semiconductors with the same high surface area morphologies but composed of a material having more desirable electronic properties. A polymer can be applied over the surface of the ZnO nanorod films before etching the ZnO with a weak acid, thereby leaving a polymer nanopore membrane. Cathodic electrodeposition of Cu2O into the membrane nanopores gives Cu2O nanorods. Electron-accepting dyes are designed with tethers that allow for direct attachment to metal oxide semiconductors. After soaking, the semiconductor is coated with a monolayer of a dye and then the coated semiconductor films were made into various dye-sensitized solar cells (DSCs). These cells were studied to determine the electron transport properties at the semiconductor/sensitizer/electrolyte interface.

Advances in data-driven applications, particularly artificial intelligence and deep learning, are driving the explosive growth of computation and communication in today’s data centers and high-performance computing (HPC) systems. Increasingly, system performance is not constrained by the compute speed at individual nodes, but by the data movement between them. This calls for innovative architectures, smart connectivity, and extreme bandwidth densities in interconnect designs. Silicon photonics technology leverages mature complementary metal-oxide-semiconductor (CMOS) manufacturing infrastructure and is promising for low cost, high-bandwidth, and reconfigurable interconnects. Flexible and high-performance photonic switched architectures are capable of improving the system performance. The work in this dissertation explores various photonic interconnected systems and the associated optical switching functionalities, hardware platforms, and novel architectures. It demonstrates the capabilities of silicon photonics to enable efficient deep learning training. We first present field programmable gate array (FPGA) based open-loop and closed-loop control for optical spectral-and-spatial switching of silicon photonic cascaded micro-ring resonator (MRR) switches. Our control achieves wavelength locking at the user-defined resonance of the MRR for optical unicast, multicast, and multiwavelength-select functionalities. Digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) are necessary for the control of the switch. We experimentally demonstrate the optical switching functionalities using an FPGA-based switch controller through both traditional multi-bit DAC/ADC and novel single-wired DAC/ADC circuits. For system-level integration, interfaces to the switch controller in a network control plane are developed. The successful control and the switching functionalitiesachieved are essential for system-level architectural innovations as presented in the following sections. Next, this thesis presents two novel photonic switched architectures using the MRR-based switches. First, a photonic switched memory system architecture was designed to address memory challenges in deep learning. The reconfigurable photonic interconnects provide scalable solutions and enable efficient use of disaggregated memory resources for deep learning training. An experimental testbed was built with a processing system and two remote memory nodes using silicon photonic switch fabrics and system performance improvements were demonstrated. The collective results and existing high-bandwidth optical I/Os show the potential of integrating the photonic switched memory to state-of-the-art processing systems. Second, the scaling trends of deep learning models and distributed training workloads are challenging network capacities in today’s data centers and HPCs. A system architecture that leverages SiP switch-enabled server regrouping is proposed to tackle the challenges and accelerate distributed deep learning training. An experimental testbed with a SiP switch-enabled reconfigurable fat tree topology was built to evaluate the network performance of distributed ring all-reduce and parameter server workloads. We also present system-scale simulations. Server regrouping and bandwidth steering were performed on a large-scale tapered fat tree with 1024 compute nodes to show the benefits of using photonic switched architectures in systems at scale. Finally, this dissertation explores high-bandwidth photonic interconnect designs for disaggregated systems. We first introduce and discuss two disaggregated architectures leveraging extreme high bandwidth interconnects with optically interconnected computing resources. We present the concept of rack-scale graphics processing unit (GPU) disaggregation with optical circuit switches and electrical aggregator switches. The architecture can leverage the flexibility of high bandwidth optical switches to increase hardware utilization and reduce application runtimes. A testbed was built to demonstrate resource disaggregation and defragmentation. In addition, we also present an extreme high-bandwidth optical interconnect accelerated low-latency communication architecture for deep learning training. The disaggregated architecture utilizes comb laser sources and MRR-based cross-bar switching fabrics to enable an all-to-all high bandwidth communication with a constant latency cost for distributed deep learning training. We discuss emerging technologies in the silicon photonics platform, including light source, transceivers, and switch architectures, to accommodate extreme high bandwidth requirements in HPC and data center environments. A prototype hardware innovation - Optical Network Interface Cards (comprised of FPGA, photonic integrated circuits (PIC), electronic integrated circuits (EIC), interposer, and high-speed printed circuit board (PCB)) is presented to show the path toward fast lanes for expedited execution at 10 terabits. Taken together, the work in this dissertation demonstrates the capabilities of high-bandwidth silicon photonic interconnects and innovative architectural designs to accelerate deep learning training in optically connected data center and HPC systems.