Spelling suggestions: "subject:"metaloxidesemiconductor"" "subject:"metalâoxideâsemiconductor""
121 |
Design and Application of SiC Power MOSFETLinewih, Handoko, h.linewih@griffith.edu.au January 2003 (has links)
This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.
|
122 |
Systematic evaluation of metal gate electrode effective work function and its influence on device performance in CMOS devicesWen, Huang-Chun, January 1900 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.
|
123 |
Design and simulation of strained-Si/strained SiGe dual channel hetero-structure MOSFETs /Goyal, Puneet. January 2007 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 2007. / Typescript. Includes bibliographical references.
|
124 |
Ultra low voltage DRAM current sense amplifier with body bias techniquesGang, Yung-jin, 1957- 23 November 1998 (has links)
The major limiting factor of DRAM access time is the low transconductance of the
MOSFET's which have only limited current drive capability. The bipolar junction
transistor(BJT) has a collector current amplification factor, ��, times base current and is
limited mostly by the willingness to supply this base current. This collector current is
much larger than the MOSFET drain current under similar conditions. The requirements
for low power and low power densities results in lower power supply voltages which are
also inconsistent with the threshold voltage variations in CMOS technology, as a
consequence at least pulsed body bias or synchronous body bias will probably be
utilized. Given that of the CMOS body will be driven or the CMOS gate and body
connected a BJT technique is proposed for ultra low voltages like Vdd=0.5. Utilizing
present CMOS process technology good results can be achieved with ultra low power
using gate-body connected transistors and a current sense amplifier. / Graduation date: 1999
|
125 |
CMOS low noise amplifier design utilizing monolithic transformersZhou, Jianjun J. 18 August 1998 (has links)
Full integration of CMOS low noise amplifiers (LNA) presents a challenge for low
cost CMOS receiver systems. A critical problem faced in the design of an RF CMOS LNA
is the inaccurate high-frequency noise model of the MOSFET implemented in circuit
simulators such as SPICE. Silicon-based monolithic inductors are another bottleneck in RF
CMOS design due to their poor quality factor.
In this thesis, a CMOS implementation of a fully-integrated differential LNA is
presented. A small-signal noise circuit model that includes the two most important noise
sources of the MOSFET at radio frequencies, channel thermal noise and induced gate
current noise, is developed for CMOS LNA analysis and simulation. Various CMOS LNA
architectures are investigated. The optimization techniques and design guidelines and
procedures for an LC tuned CMOS LNA are also described.
Analysis and modeling of silicon-based monolithic inductors and transformers are
presented and it is shown that in fully-differential applications, a monolithic transformer
occupies less die area and achieves a higher quality factor compared to two independent
inductors with the same total effective inductance. It is also shown that monolithic
transformers improve the common-mode rejection of the differential circuits. / Graduation date: 1999
|
126 |
MOSFET-only predictive track and hold circuitQiu, Xiangping 19 March 1997 (has links)
High-accuracy and high-speed CMOS track-and-hold (T/H) or sample-and-hold (S/H) circuits are an important part of the analog-to-digital interface. The switched-capacitor (SC) circuits usually contain one or more op-amps whose dc offset, finite gain, finite bandwidth have a big impact on the accuracy of the track-and-hold circuit. Basic correlated double sampling (CDS) scheme can reduce such effects, but the compensation that it provides may not be good enough for high-accuracy application. Also, the high-quality analog poly-poly capacitors used in most SC circuits are not available in a basic digital CMOS process. The MOSFET-only predictive track-and-hold circuit, discussed in this thesis, replaces the poly-poly capacitors with easily-available low-cost area-saving MOSFET capacitors biased in accumulation region. It also uses the predictive correlated double sampling (CDS) scheme, in which the op-amp
predicts its output for the next clock period during the present clock period, so that the adjacent two output samples are nearly the same. The predictive operation results in more correlation between the unwanted signal and the signal that is subtracted during the double sampling, and hence can achieve offset and gain compensation over wider frequency range. Hence, this circuit is suitable for high-accuracy applications, while using only a basic digital process. / Graduation date: 1997
|
127 |
Poly-Si₁âxGex Film Growth for Ni Germanosilicided Metal Gate / Poly-Si1-xGex Film Growth for Ni Germanosilicided Metal GateYu, Hongpeng, Pey, Kin Leong, Choi, Wee Kiong, Fitzgerald, Eugene A., Antoniadis, Dimitri A. 01 1900 (has links)
Scaling down of the CMOS technology requires thinner gate dielectric to maintain high performance. However, due to the depletion of poly-Si gate, it is difficult to reduce the gate thickness further especially for sub-65 nm CMOS generation. Fully silicidation metal gate (FUSI) is one of the most promising solutions. Furthermore, FUSI metal gate reduces gate-line sheet resistance, prevents boron penetration to channels, and has good process compatibility with high-k gate dielectric. Poly-SiGe gate technology is another solution because of its enhancement of boron activation and compatibility with the conventional CMOS process. Combination of these two technologies for the formation of fully germanosilicided metal gate makes the approach very attractive. In this paper, the deposition of undoped Poly-Si₁âxGex (0 < x < 30% ) films onto SiO₂ in a low pressure chemical vapor deposition (LPCVD) system is described. Detailed growth conditions and the characterization of the grown films are presented. / Singapore-MIT Alliance (SMA)
|
128 |
Characterization of Transistor Matching in Silicon-Germanium Heterojunction Bipolar TransistorsPratapgarhwala, Mustansir M. 23 November 2005 (has links)
Transistor mismatch is a crucial design issue in high precision analog circuits, and is investigated here for the first time in SiGe HBTs. The goal of this work is to study the effects of mismatch under extreme conditions including radiation, high temperature, and low temperature.
One portion of this work reports collector current mismatch data as a function of emitter geometry both before and after 63 MeV proton exposure for first-generation SiGe HBTs with a peak cut-off frequency of 60 GHz. However, minimal changes in device-to-device mismatch after radiation exposure were experienced.
Another part of the study involved measuring similar devices at different temperatures ranging from 298K to 377K. As a general trend, it was observed that device-to-device mismatch improved with increasing temperature.
|
129 |
Enhanced hot-hole degradation and negative bias temperature instability (NBTI) in p⁺-poly PMOSFETs with oxynitride gate dielectrics /Chen, Yuh-yue, January 2000 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 158-172). Available also in a digital version from Dissertation Abstracts.
|
130 |
Strain effects on the valence band of silicon piezoresistance in p-type silicon and mobility enhancement in strained silicon pMOSFET /Wu, Kehuey. January 2005 (has links)
Thesis (Ph. D.)--University of Florida, 2005. / Title from title page of source document. Document formatted into pages; contains 157 pages. Includes vita. Includes bibliographical references.
|
Page generated in 0.0655 seconds